| Message ID | 20221222151319.122398-4-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v4,1/4] arm64: dts: qcom: sdm845-db845c: fix audio codec interrupt pin name | expand |
On 22.12.2022 16:13, Krzysztof Kozlowski wrote: > Each board should define pin drive/bias for used busses. All boards > using SPI0 (db845c and cheza) already do it, so drop the bias/drive > strength from SoC DTSI. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > > Cc: Doug Anderson <dianders@chromium.org> > > Changes since v3: > 1. Rb tag > > Changes since v2: > 1. New patch. > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index dcea535de9b7..cac70212cc2a 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -2785,8 +2785,6 @@ qup_i2c15_default: qup-i2c15-default-state { > qup_spi0_default: qup-spi0-default-state { > pins = "gpio0", "gpio1", "gpio2", "gpio3"; > function = "qup0"; > - drive-strength = <6>; > - bias-disable; > }; > > qup_spi1_default: qup-spi1-default-state {
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index dcea535de9b7..cac70212cc2a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2785,8 +2785,6 @@ qup_i2c15_default: qup-i2c15-default-state { qup_spi0_default: qup-spi0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; - drive-strength = <6>; - bias-disable; }; qup_spi1_default: qup-spi1-default-state {