| Message ID | 20221229100511.979972-2-konrad.dybcio@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2,1/3] dt-bindings: display/msm: Add SM8150 MDSS & DPU | expand |
On Thu, 29 Dec 2022 at 12:05, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > Years after the SoC support has been added, it's high time for it to > get dispcc going. Add the node to ensure that. > > Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5 > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > v1 -> v2: > - Pick up tags > - Remove required-opps > - Move power-domains up > arch/arm64/boot/dts/qcom/sm8150.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index a0c57fb798d3..c7935f7a2926 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -3579,6 +3579,29 @@ camnoc_virt: interconnect@ac00000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + dispcc: clock-controller@af00000 { > + compatible = "qcom,sm8150-dispcc"; > + reg = <0 0x0af00000 0 0x10000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_byteclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk"; > + power-domains = <&rpmhpd SM8150_MMCX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8150-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x400>; > -- > 2.39.0 >
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..c7935f7a2926 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3579,6 +3579,29 @@ camnoc_virt: interconnect@ac00000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SM8150_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x400>;