| Message ID | 20221209-dt-binding-ufs-v2-1-dc7a04699579@fairphone.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix some issues in QCOM UFS bindings | expand |
On 30.12.2022 08:42, Luca Weiss wrote: > The UFS driver expects the second reg to be named "ice" otherwise the > Inline Crypto Engine won't get enabled. > > Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=01b6041454e8bc4f5feb76e6bcdc83a48cea21f2 Konrad > arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 572bf04adf90..85673d562723 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -704,6 +704,7 @@ opp-202000000 { > ufs_mem_hc: ufs@4804000 { > compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > reg = <0x04804000 0x3000>, <0x04810000 0x8000>; > + reg-names = "std", "ice"; > interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > phys = <&ufs_mem_phy_lanes>; > phy-names = "ufsphy"; >
On Fri Dec 30, 2022 at 10:12 AM CET, Konrad Dybcio wrote: > > > On 30.12.2022 08:42, Luca Weiss wrote: > > The UFS driver expects the second reg to be named "ice" otherwise the > > Inline Crypto Engine won't get enabled. > > > > Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > > --- > > https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=01b6041454e8bc4f5feb76e6bcdc83a48cea21f2 Oh, thanks! Disregard this patch then please. > > Konrad > > arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > index 572bf04adf90..85673d562723 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > > @@ -704,6 +704,7 @@ opp-202000000 { > > ufs_mem_hc: ufs@4804000 { > > compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > > reg = <0x04804000 0x3000>, <0x04810000 0x8000>; > > + reg-names = "std", "ice"; > > interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > > phys = <&ufs_mem_phy_lanes>; > > phy-names = "ufsphy"; > >
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 572bf04adf90..85673d562723 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -704,6 +704,7 @@ opp-202000000 { ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy";
The UFS driver expects the second reg to be named "ice" otherwise the Inline Crypto Engine won't get enabled. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+)