| Message ID | 20221230075726.122806-1-duke_xinanwen@163.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | bus: mhi: host: pci_generic: Add support for Quectel RM520N-GL modem | expand |
Hi Duke, On Fri, 30 Dec 2022 at 08:57, Duke Xin(辛安文) <duke_xinanwen@163.com> wrote: > > The project is based on Qualcomm's sdx6x chips for laptop,so the mhi interface definition and > enumeration align with previous Quectel sdx24 configuration > > Signed-off-by: Duke Xin(辛安文) <duke_xinanwen@163.com> > --- > drivers/bus/mhi/host/pci_generic.c | 46 ++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > index f39657f71483..83f40617af9a 100644 > --- a/drivers/bus/mhi/host/pci_generic.c > +++ b/drivers/bus/mhi/host/pci_generic.c > @@ -335,6 +335,50 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { > .sideband_wake = true, > }; > > +static const struct mhi_channel_config mhi_quectel_rm5xx_channels[] = { > + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), > + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), > + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), > + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), > + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), > + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), > + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), > + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), > + /* The EDL firmware is a flash-programmer exposing firehose protocol */ > + MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), > + MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), > + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), > + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), > +}; > + > +static struct mhi_event_config mhi_quectel_rm5xx_events[] = { > + MHI_EVENT_CONFIG_CTRL(0, 128), > + MHI_EVENT_CONFIG_DATA(1, 128), > + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), > + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) > +}; > + > +static const struct mhi_controller_config modem_quectel_rm5xx_config = { > + .max_channels = 128, > + .timeout_ms = 20000, > + .num_channels = ARRAY_SIZE(mhi_quectel_rm5xx_channels), > + .ch_cfg = mhi_quectel_rm5xx_channels, > + .num_events = ARRAY_SIZE(mhi_quectel_rm5xx_events), > + .event_cfg = mhi_quectel_rm5xx_events, > +}; > + > +static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { > + .name = "quectel-rm5xx", > + .edl = "qcom/prog_firehose_sdx6x.elf", > + .config = &modem_quectel_rm5xx_config, Use `modem_quectel_em1xx_config` if compatible instead of duplicating the configuration. Regards, Loic
diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index f39657f71483..83f40617af9a 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -335,6 +335,50 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { .sideband_wake = true, }; +static const struct mhi_channel_config mhi_quectel_rm5xx_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), + /* The EDL firmware is a flash-programmer exposing firehose protocol */ + MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), + MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), +}; + +static struct mhi_event_config mhi_quectel_rm5xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 128), + MHI_EVENT_CONFIG_DATA(1, 128), + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) +}; + +static const struct mhi_controller_config modem_quectel_rm5xx_config = { + .max_channels = 128, + .timeout_ms = 20000, + .num_channels = ARRAY_SIZE(mhi_quectel_rm5xx_channels), + .ch_cfg = mhi_quectel_rm5xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_rm5xx_events), + .event_cfg = mhi_quectel_rm5xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { + .name = "quectel-rm5xx", + .edl = "qcom/prog_firehose_sdx6x.elf", + .config = &modem_quectel_rm5xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .mru_default = 32768, + .sideband_wake = true, +}; + static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), @@ -569,6 +613,8 @@ static const struct pci_device_id mhi_pci_id_table[] = { .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), /* RM520N-GL (sdx6x) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
The project is based on Qualcomm's sdx6x chips for laptop,so the mhi interface definition and enumeration align with previous Quectel sdx24 configuration Signed-off-by: Duke Xin(辛安文) <duke_xinanwen@163.com> --- drivers/bus/mhi/host/pci_generic.c | 46 ++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)