| Message ID | 20221221-ira-cxl-events-2022-11-17-v2-7-2ce2ecc06219@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU CXL Provide mock CXL events and irq support | expand |
On Wed, 21 Dec 2022 20:24:37 -0800 Ira Weiny <ira.weiny@intel.com> wrote: > CXL has 24 bit unaligned fields which need to be stored to. CXL is > specified as little endian. > > Define st24_le_p() and the supporting functions to store such a field > from a 32 bit host native value. > > The use of b, w, l, q as the size specifier is limiting. So "24" was > used for the size part of the function name. > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> Hi Ira, Whilst this seems good to me, it's buried deep in a CXL specific patch set so I'm thinking it might not get the review it needs. Perhaps we are better off starting with a local implementation then posting a follow up series that introduces this an makes use of it in the CXL code? One comment inline. Jonathan > --- > include/qemu/bswap.h | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h > index e1eca22f2548..8af4d4a75eb6 100644 > --- a/include/qemu/bswap.h > +++ b/include/qemu/bswap.h > @@ -25,6 +25,13 @@ static inline uint16_t bswap16(uint16_t x) > return bswap_16(x); > } > > +static inline uint32_t bswap24(uint32_t x) > +{ > + return (((x & 0x000000ffU) << 16) | > + ((x & 0x0000ff00U) << 0) | > + ((x & 0x00ff0000U) >> 16)); > +} > + > static inline uint32_t bswap32(uint32_t x) > { > return bswap_32(x); > @@ -43,6 +50,13 @@ static inline uint16_t bswap16(uint16_t x) > ((x & 0xff00) >> 8)); > } > > +static inline uint32_t bswap24(uint32_t x) > +{ > + return (((x & 0x000000ffU) << 16) | > + ((x & 0x0000ff00U) << 0) | > + ((x & 0x00ff0000U) >> 16)); > +} Whilst I can see the logic in having two copies to keep it in a sensible place wrt to the other implementations, neither of these is from byteswap so I'd just drop it out of the ifdef and have just the one copy. > + > static inline uint32_t bswap32(uint32_t x) > { > return (((x & 0x000000ffU) << 24) | > @@ -72,6 +86,11 @@ static inline void bswap16s(uint16_t *s) > *s = bswap16(*s); > } > > +static inline void bswap24s(uint32_t *s) > +{ > + *s = bswap24(*s); > +} > + > static inline void bswap32s(uint32_t *s) > { > *s = bswap32(*s); > @@ -233,6 +252,7 @@ CPU_CONVERT(le, 64, uint64_t) > * size is: > * b: 8 bits > * w: 16 bits > + * 24: 24 bits > * l: 32 bits > * q: 64 bits > * > @@ -305,6 +325,11 @@ static inline void stw_he_p(void *ptr, uint16_t v) > __builtin_memcpy(ptr, &v, sizeof(v)); > } > > +static inline void st24_he_p(void *ptr, uint32_t v) > +{ > + __builtin_memcpy(ptr, &v, 3); > +} > + > static inline int ldl_he_p(const void *ptr) > { > int32_t r; > @@ -354,6 +379,11 @@ static inline void stw_le_p(void *ptr, uint16_t v) > stw_he_p(ptr, le_bswap(v, 16)); > } > > +static inline void st24_le_p(void *ptr, uint32_t v) > +{ > + st24_he_p(ptr, le_bswap(v, 24)); > +} > + > static inline void stl_le_p(void *ptr, uint32_t v) > { > stl_he_p(ptr, le_bswap(v, 32)); >
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index e1eca22f2548..8af4d4a75eb6 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -25,6 +25,13 @@ static inline uint16_t bswap16(uint16_t x) return bswap_16(x); } +static inline uint32_t bswap24(uint32_t x) +{ + return (((x & 0x000000ffU) << 16) | + ((x & 0x0000ff00U) << 0) | + ((x & 0x00ff0000U) >> 16)); +} + static inline uint32_t bswap32(uint32_t x) { return bswap_32(x); @@ -43,6 +50,13 @@ static inline uint16_t bswap16(uint16_t x) ((x & 0xff00) >> 8)); } +static inline uint32_t bswap24(uint32_t x) +{ + return (((x & 0x000000ffU) << 16) | + ((x & 0x0000ff00U) << 0) | + ((x & 0x00ff0000U) >> 16)); +} + static inline uint32_t bswap32(uint32_t x) { return (((x & 0x000000ffU) << 24) | @@ -72,6 +86,11 @@ static inline void bswap16s(uint16_t *s) *s = bswap16(*s); } +static inline void bswap24s(uint32_t *s) +{ + *s = bswap24(*s); +} + static inline void bswap32s(uint32_t *s) { *s = bswap32(*s); @@ -233,6 +252,7 @@ CPU_CONVERT(le, 64, uint64_t) * size is: * b: 8 bits * w: 16 bits + * 24: 24 bits * l: 32 bits * q: 64 bits * @@ -305,6 +325,11 @@ static inline void stw_he_p(void *ptr, uint16_t v) __builtin_memcpy(ptr, &v, sizeof(v)); } +static inline void st24_he_p(void *ptr, uint32_t v) +{ + __builtin_memcpy(ptr, &v, 3); +} + static inline int ldl_he_p(const void *ptr) { int32_t r; @@ -354,6 +379,11 @@ static inline void stw_le_p(void *ptr, uint16_t v) stw_he_p(ptr, le_bswap(v, 16)); } +static inline void st24_le_p(void *ptr, uint32_t v) +{ + st24_he_p(ptr, le_bswap(v, 24)); +} + static inline void stl_le_p(void *ptr, uint32_t v) { stl_he_p(ptr, le_bswap(v, 32));
CXL has 24 bit unaligned fields which need to be stored to. CXL is specified as little endian. Define st24_le_p() and the supporting functions to store such a field from a 32 bit host native value. The use of b, w, l, q as the size specifier is limiting. So "24" was used for the size part of the function name. Signed-off-by: Ira Weiny <ira.weiny@intel.com> --- include/qemu/bswap.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)