| Message ID | 20230103203654.59322-4-nick.hawkins@hpe.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | ARM: Add GXP Fan and SPI controllers | expand |
On Tue, Jan 03, 2023 at 02:36:52PM -0600, nick.hawkins@hpe.com wrote: > From: Nick Hawkins <nick.hawkins@hpe.com> > > Reorganize the base address of AHB to accommodate the SPI and fan driver > register requirements. Add the hpe,gxp-spifi and hpe,gxp-fan-ctrl > compatibles. Add comments to make the register range more clear. > > Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Note that I can not apply this patch; it will have to be applied through the arm tree. Guenter > --- > v4: > *No change > v3: > *No change > v2: > *Changed fn2reg to fn2 > *Changed plreg to pl > *Changed fanctrl to fan-controller > *Adjusted base register range to elminate need for defines in code > --- > arch/arm/boot/dts/hpe-bmc-dl360gen10.dts | 58 +++++++++++++++++++++ > arch/arm/boot/dts/hpe-gxp.dtsi | 64 +++++++++++++++++------- > 2 files changed, 103 insertions(+), 19 deletions(-) > > diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts > index 3a7382ce40ef..d49dcef95c5c 100644 > --- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts > +++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts > @@ -24,3 +24,61 @@ > reg = <0x40000000 0x20000000>; > }; > }; > + > +&spifi { > + status = "okay"; > + flash@0 { > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + u-boot@0 { > + label = "u-boot"; > + reg = <0x0 0x60000>; > + }; > + > + u-boot-env@60000 { > + label = "u-boot-env"; > + reg = <0x60000 0x20000>; > + }; > + > + kernel@80000 { > + label = "kernel"; > + reg = <0x80000 0x4c0000>; > + }; > + > + rofs@540000 { > + label = "rofs"; > + reg = <0x540000 0x1740000>; > + }; > + > + rwfs@1c80000 { > + label = "rwfs"; > + reg = <0x1c80000 0x250000>; > + }; > + > + section@1ed0000{ > + label = "section"; > + reg = <0x1ed0000 0x130000>; > + }; > + }; > + }; > + flash@1 { > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + host-prime@0 { > + label = "host-prime"; > + reg = <0x0 0x02000000>; > + }; > + > + host-second@2000000 { > + label = "host-second"; > + reg = <0x02000000 0x02000000>; > + }; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi > index cf735b3c4f35..b73b22a93716 100644 > --- a/arch/arm/boot/dts/hpe-gxp.dtsi > +++ b/arch/arm/boot/dts/hpe-gxp.dtsi > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Device Tree file for HPE GXP > + * Device Tree for HPE > */ > > /dts-v1/; > @@ -52,76 +52,102 @@ > cache-level = <2>; > }; > > - ahb@c0000000 { > + ahb@80000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0x0 0xc0000000 0x30000000>; > + ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ > + <0x40000000 0xc0000000 0x7fffffff>; /* 0xc0000000 - 0xffffffff */ > dma-ranges; > > - vic0: interrupt-controller@eff0000 { > + spifi: spi@40000200 { /* 0xc0000200 */ > + compatible = "hpe,gxp-spifi"; > + reg = <0x40000200 0x80>, <0x4000c000 0x100>, <0x78000000 0x7ff0000>; > + interrupts = <20>; > + interrupt-parent = <&vic0>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + flash@0 { > + reg = <0>; > + compatible = "jedec,spi-nor"; > + }; > + > + flash@1 { > + reg = <1>; > + compatible = "jedec,spi-nor"; > + }; > + }; > + > + vic0: interrupt-controller@4eff0000 { /* 0xceff0000 */ > compatible = "arm,pl192-vic"; > - reg = <0xeff0000 0x1000>; > + reg = <0x4eff0000 0x1000>; > interrupt-controller; > #interrupt-cells = <1>; > }; > > - vic1: interrupt-controller@80f00000 { > + vic1: interrupt-controller@f00000 { /* 0x80f00000 */ > compatible = "arm,pl192-vic"; > - reg = <0x80f00000 0x1000>; > + reg = <0xf00000 0x1000>; > interrupt-controller; > #interrupt-cells = <1>; > }; > > - uarta: serial@e0 { > + uarta: serial@400000e0 { /* 0xc00000e0 */ > compatible = "ns16550a"; > - reg = <0xe0 0x8>; > + reg = <0x400000e0 0x8>; > interrupts = <17>; > interrupt-parent = <&vic0>; > clock-frequency = <1846153>; > reg-shift = <0>; > }; > > - uartb: serial@e8 { > + uartb: serial@400000e8 { /* 0xc00000e8 */ > compatible = "ns16550a"; > - reg = <0xe8 0x8>; > + reg = <0x400000e8 0x8>; > interrupts = <18>; > interrupt-parent = <&vic0>; > clock-frequency = <1846153>; > reg-shift = <0>; > }; > > - uartc: serial@f0 { > + uartc: serial@400000f0 { /* 0xc00000f0 */ > compatible = "ns16550a"; > - reg = <0xf0 0x8>; > + reg = <0x400000f0 0x8>; > interrupts = <19>; > interrupt-parent = <&vic0>; > clock-frequency = <1846153>; > reg-shift = <0>; > }; > > - usb0: usb@efe0000 { > + usb0: usb@4efe0000 { /* 0xcefe0000 */ > compatible = "hpe,gxp-ehci", "generic-ehci"; > - reg = <0xefe0000 0x100>; > + reg = <0x4efe0000 0x100>; > interrupts = <7>; > interrupt-parent = <&vic0>; > }; > > - st: timer@80 { > + st: timer@40000080 { /* 0xc0000080 */ > compatible = "hpe,gxp-timer"; > - reg = <0x80 0x16>; > + reg = <0x40000080 0x16>; > interrupts = <0>; > interrupt-parent = <&vic0>; > clocks = <&iopclk>; > clock-names = "iop"; > }; > > - usb1: usb@efe0100 { > + usb1: usb@4efe0100 { /* 0xcefe0100 */ > compatible = "hpe,gxp-ohci", "generic-ohci"; > - reg = <0xefe0100 0x110>; > + reg = <0x4efe0100 0x110>; > interrupts = <6>; > interrupt-parent = <&vic0>; > }; > + > + fan-controller@40000c10 { /* 0xc0000c10 */ > + compatible = "hpe,gxp-fan-ctrl"; > + reg = <0x40000c10 0x8>, <0x51000027 0x06>, <0x200070 0x04>; > + reg-names = "base", "pl", "fn2"; > + }; > }; > }; > };
On Tue, Jan 3, 2023, at 21:36, nick.hawkins@hpe.com wrote: > From: Nick Hawkins <nick.hawkins@hpe.com> > > Reorganize the base address of AHB to accommodate the SPI and fan driver > register requirements. Add the hpe,gxp-spifi and hpe,gxp-fan-ctrl > compatibles. Add comments to make the register range more clear. > > Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> > > diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi > b/arch/arm/boot/dts/hpe-gxp.dtsi > index cf735b3c4f35..b73b22a93716 100644 > --- a/arch/arm/boot/dts/hpe-gxp.dtsi > +++ b/arch/arm/boot/dts/hpe-gxp.dtsi > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Device Tree file for HPE GXP > + * Device Tree for HPE > */ > > /dts-v1/; > @@ -52,76 +52,102 @@ > cache-level = <2>; > }; > > - ahb@c0000000 { > + ahb@80000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0x0 0xc0000000 0x30000000>; > + ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ > + <0x40000000 0xc0000000 0x7fffffff>; /* 0xc0000000 - 0xffffffff */ I'm a bit confused by the change in the mappings: are you sure this all the same ahb bus and not two separate buses? The comment for the second range looks wrong to me, as you define a 2GB (minus one byte) sized mapping but the comment only lists a 1GB (including the last byte) mapping. I would expect that the original 0x30000000 (including the last byte) was correct here. > - vic1: interrupt-controller@80f00000 { > + vic1: interrupt-controller@f00000 { /* 0x80f00000 */ This is not the same address as before. I'm also not sure the comment is helpful here. Arnd
> > - ahb@c0000000 { > > + ahb@80000000 { > > compatible = "simple-bus"; > > #address-cells = <1>; > > #size-cells = <1>; > > - ranges = <0x0 0xc0000000 0x30000000>; > > + ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ > > + <0x40000000 0xc0000000 0x7fffffff>; /* 0xc0000000 - 0xffffffff */ > I'm a bit confused by the change in the mappings: are you > sure this all the same ahb bus and not two separate buses? Yes this is the same bus, however we are not including all of it as it maps some host registers that we do not want to access at this time. > The comment for the second range looks wrong to me, as > you define a 2GB (minus one byte) sized mapping but the > comment only lists a 1GB (including the last byte) mapping. > I would expect that the original 0x30000000 (including the > last byte) was correct here. Yes this was incorrect, I believe it should be: ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ <0x40000000 0xc0000000 0x3fffffff>; /* 0xc0000000 - 0xffffffff */ I will create a v5 version of this patchset with just this and the defconfig for your review. > > - vic1: interrupt-controller@80f00000 { > > + vic1: interrupt-controller@f00000 { /* 0x80f00000 */ > This is not the same address as before. I'm also not sure the > comment is helpful here. My understanding was that the physical address would be the 0x80000000 from the first range plus the 0xf00000 to be 0x80f00000? Thank you, -Nick Hawkins
On Thu, Jan 12, 2023, at 16:40, Hawkins, Nick wrote: >> > - ahb@c0000000 { >> > + ahb@80000000 { >> > compatible = "simple-bus"; >> > #address-cells = <1>; >> > #size-cells = <1>; >> > - ranges = <0x0 0xc0000000 0x30000000>; >> > + ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ >> > + <0x40000000 0xc0000000 0x7fffffff>; /* 0xc0000000 - 0xffffffff */ > > >> I'm a bit confused by the change in the mappings: are you >> sure this all the same ahb bus and not two separate buses? > > Yes this is the same bus, however we are not including all of > it as it maps some host registers that we do not want to access > at this time. If the two ranges are actually translated separately on the bus, you could also decide to enumerate the translations with a 64-bit local address and make the upper word an enumeration, such as ranges = <0x1 0x0 0x80000000 0xf000000>, <0x2 0x0 0xc0000000 0x30000000>; then you get small numbers again in the 'reg' properties that are easier to read and ideally match the bus-local numbers from the hardware manual. >> The comment for the second range looks wrong to me, as >> you define a 2GB (minus one byte) sized mapping but the >> comment only lists a 1GB (including the last byte) mapping. > > >> I would expect that the original 0x30000000 (including the >> last byte) was correct here. > > Yes this was incorrect, I believe it should be: > > ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ > <0x40000000 0xc0000000 0x3fffffff>; /* 0xc0000000 - > 0xffffffff */ > > I will create a v5 version of this patchset with just this and the > defconfig for your review. Now it almost matches, except for the final byte, as the range actually ends at 0xfffffffe not 0xffffffff if you make the size one byte less than 1GB. Is there a special register in the last byte? >> > - vic1: interrupt-controller@80f00000 { >> > + vic1: interrupt-controller@f00000 { /* 0x80f00000 */ > > >> This is not the same address as before. I'm also not sure the >> comment is helpful here. > > My understanding was that the physical address would be the > 0x80000000 from the first range plus the 0xf00000 to be > 0x80f00000? I suppose the physical address in the old mapping was actually outside of the 0xc0000000-0xefffffff range, so it wasn't even accessible. If the addresses are interpreted to wrap around at the end of the mapping, that would have made the CPU visible address 0xe0f00000 (0xc0000000 + (0x80f00000 % 0x30000000)). If it just wrapped around as a 32-bit number, it would be 0x40f00000 ((0xc0000000 + 0x80f00000)% 0x100000000), but I don't see you you'd get to 80f00000. Arnd
> If the two ranges are actually translated separately on the > bus, you could also decide to enumerate the translations with > a 64-bit local address and make the upper word an enumeration, > such as > ranges = <0x1 0x0 0x80000000 0xf000000>, > <0x2 0x0 0xc0000000 0x30000000>; I am not finding a good example on how this would affect the node addresses and reg properties. I believe I will stick with the current format if that is acceptable. > Now it almost matches, except for the final byte, as the > range actually ends at 0xfffffffe not 0xffffffff if you make > the size one byte less than 1GB. > Is there a special register in the last byte? No there is not I will now have ranges as: ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ <0x40000000 0xc0000000 0x40000000>; /* 0xc0000000 - 0xffffffff */ > I suppose the physical address in the old mapping was actually > outside of the 0xc0000000-0xefffffff range, so it wasn't > even accessible. If the addresses are interpreted to wrap around > at the end of the mapping, that would have made the CPU visible > address 0xe0f00000 (0xc0000000 + (0x80f00000 % 0x30000000)). > If it just wrapped around as a 32-bit number, it would be > 0x40f00000 ((0xc0000000 + 0x80f00000)% 0x100000000), but I > don't see you you'd get to 80f00000. It was not intended to wrap around; it was an error before and was not accessible. The updated section of the device tree will be: ahb@80000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ <0x40000000 0xc0000000 0x40000000>; /* 0xc0000000 - 0xffffffff */ dma-ranges; ... vic0: interrupt-controller@4eff0000 { /* 0xceff0000 */ compatible = "arm,pl192-vic"; reg = <0x4eff0000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; vic1: interrupt-controller@f00000 { /* 0x80f00000 */ compatible = "arm,pl192-vic"; reg = <0xf00000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; ... }; Thanks, -Nick Hawkins
On Thu, Jan 12, 2023, at 20:58, Hawkins, Nick wrote: > The updated section of the device tree will be: > > ahb@80000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x0 0x80000000 0xf000000>, /* > 0x80000000 - 0x8f000000 */ > <0x40000000 0xc0000000 0x40000000>; /* > 0xc0000000 - 0xffffffff */ > dma-ranges; Ok > > ... > > vic0: interrupt-controller@4eff0000 { /* 0xceff0000 */ > compatible = "arm,pl192-vic"; > reg = <0x4eff0000 0x1000>; > interrupt-controller; > #interrupt-cells = <1>; > }; > > vic1: interrupt-controller@f00000 { /* 0x80f00000 */ > compatible = "arm,pl192-vic"; > reg = <0xf00000 0x1000>; > interrupt-controller; > #interrupt-cells = <1>; > }; I still don't see the value of the /* 0x80f00000 */ comments, you should define the ranges to the most sensible mapping based on the datasheet so you don't need the comments. If the datasheet uses a bus-local address (0xf00000), then just get rid of the comment, since that only adds confusion. OTOH if the 0x80f00000 number is what is in the datasheet, then adjust the ranges to do a 1:1 mapping of the registers on the bus and use that address directly. Arnd
diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts index 3a7382ce40ef..d49dcef95c5c 100644 --- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts +++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts @@ -24,3 +24,61 @@ reg = <0x40000000 0x20000000>; }; }; + +&spifi { + status = "okay"; + flash@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + label = "u-boot"; + reg = <0x0 0x60000>; + }; + + u-boot-env@60000 { + label = "u-boot-env"; + reg = <0x60000 0x20000>; + }; + + kernel@80000 { + label = "kernel"; + reg = <0x80000 0x4c0000>; + }; + + rofs@540000 { + label = "rofs"; + reg = <0x540000 0x1740000>; + }; + + rwfs@1c80000 { + label = "rwfs"; + reg = <0x1c80000 0x250000>; + }; + + section@1ed0000{ + label = "section"; + reg = <0x1ed0000 0x130000>; + }; + }; + }; + flash@1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + host-prime@0 { + label = "host-prime"; + reg = <0x0 0x02000000>; + }; + + host-second@2000000 { + label = "host-second"; + reg = <0x02000000 0x02000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi index cf735b3c4f35..b73b22a93716 100644 --- a/arch/arm/boot/dts/hpe-gxp.dtsi +++ b/arch/arm/boot/dts/hpe-gxp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree file for HPE GXP + * Device Tree for HPE */ /dts-v1/; @@ -52,76 +52,102 @@ cache-level = <2>; }; - ahb@c0000000 { + ahb@80000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0xc0000000 0x30000000>; + ranges = <0x0 0x80000000 0xf000000>, /* 0x80000000 - 0x8f000000 */ + <0x40000000 0xc0000000 0x7fffffff>; /* 0xc0000000 - 0xffffffff */ dma-ranges; - vic0: interrupt-controller@eff0000 { + spifi: spi@40000200 { /* 0xc0000200 */ + compatible = "hpe,gxp-spifi"; + reg = <0x40000200 0x80>, <0x4000c000 0x100>, <0x78000000 0x7ff0000>; + interrupts = <20>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + }; + }; + + vic0: interrupt-controller@4eff0000 { /* 0xceff0000 */ compatible = "arm,pl192-vic"; - reg = <0xeff0000 0x1000>; + reg = <0x4eff0000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; - vic1: interrupt-controller@80f00000 { + vic1: interrupt-controller@f00000 { /* 0x80f00000 */ compatible = "arm,pl192-vic"; - reg = <0x80f00000 0x1000>; + reg = <0xf00000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; - uarta: serial@e0 { + uarta: serial@400000e0 { /* 0xc00000e0 */ compatible = "ns16550a"; - reg = <0xe0 0x8>; + reg = <0x400000e0 0x8>; interrupts = <17>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - uartb: serial@e8 { + uartb: serial@400000e8 { /* 0xc00000e8 */ compatible = "ns16550a"; - reg = <0xe8 0x8>; + reg = <0x400000e8 0x8>; interrupts = <18>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - uartc: serial@f0 { + uartc: serial@400000f0 { /* 0xc00000f0 */ compatible = "ns16550a"; - reg = <0xf0 0x8>; + reg = <0x400000f0 0x8>; interrupts = <19>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - usb0: usb@efe0000 { + usb0: usb@4efe0000 { /* 0xcefe0000 */ compatible = "hpe,gxp-ehci", "generic-ehci"; - reg = <0xefe0000 0x100>; + reg = <0x4efe0000 0x100>; interrupts = <7>; interrupt-parent = <&vic0>; }; - st: timer@80 { + st: timer@40000080 { /* 0xc0000080 */ compatible = "hpe,gxp-timer"; - reg = <0x80 0x16>; + reg = <0x40000080 0x16>; interrupts = <0>; interrupt-parent = <&vic0>; clocks = <&iopclk>; clock-names = "iop"; }; - usb1: usb@efe0100 { + usb1: usb@4efe0100 { /* 0xcefe0100 */ compatible = "hpe,gxp-ohci", "generic-ohci"; - reg = <0xefe0100 0x110>; + reg = <0x4efe0100 0x110>; interrupts = <6>; interrupt-parent = <&vic0>; }; + + fan-controller@40000c10 { /* 0xc0000c10 */ + compatible = "hpe,gxp-fan-ctrl"; + reg = <0x40000c10 0x8>, <0x51000027 0x06>, <0x200070 0x04>; + reg-names = "base", "pl", "fn2"; + }; }; }; };