| Message ID | 20230104093450.3150578-4-abel.vesa@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | ddce89cc525400fa4cc45269c9d0a7cfb30012cc |
| Headers | show |
| Series | clk: qcom: Add support for SM8550 | expand |
On 04/01/2023 11:34, Abel Vesa wrote: > Adds the RPMH clocks present in SM8550 SoC. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/clk/qcom/clk-rpmh.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) I think the plan was to have the _PAD clock as a child node of the rpmcc. Is it still the planned implementation?
On 23-01-04 12:46:55, Dmitry Baryshkov wrote: > On 04/01/2023 11:34, Abel Vesa wrote: > > Adds the RPMH clocks present in SM8550 SoC. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > --- > > drivers/clk/qcom/clk-rpmh.c | 36 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 36 insertions(+) > > I think the plan was to have the _PAD clock as a child node of the rpmcc. Is > it still the planned implementation? Yes. Here is how the dts rpmhcc node will look like: rpmhcc: clock-controller { compatible = "qcom,sm8550-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; bi_tcxo_div2: bi-tcxo-div2-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-mult = <1>; clock-div = <2>; }; bi_tcxo_ao_div2: bi-tcxo-div2-ao-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&rpmhcc RPMH_CXO_CLK_A>; clock-mult = <1>; clock-div = <2>; }; }; The clock nodes will be probed on of_clk_init. > > -- > With best wishes > Dmitry >
On 04/01/2023 14:45, Abel Vesa wrote: > On 23-01-04 12:46:55, Dmitry Baryshkov wrote: >> On 04/01/2023 11:34, Abel Vesa wrote: >>> Adds the RPMH clocks present in SM8550 SoC. >>> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>> --- >>> drivers/clk/qcom/clk-rpmh.c | 36 ++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 36 insertions(+) >> >> I think the plan was to have the _PAD clock as a child node of the rpmcc. Is >> it still the planned implementation? > > Yes. Here is how the dts rpmhcc node will look like: > > rpmhcc: clock-controller { > compatible = "qcom,sm8550-rpmh-clk"; > #clock-cells = <1>; > clock-names = "xo"; > clocks = <&xo_board>; > > bi_tcxo_div2: bi-tcxo-div2-clk { > #clock-cells = <0>; > compatible = "fixed-factor-clock"; > clocks = <&rpmhcc RPMH_CXO_CLK>; > clock-mult = <1>; > clock-div = <2>; > }; > > bi_tcxo_ao_div2: bi-tcxo-div2-ao-clk { > #clock-cells = <0>; > compatible = "fixed-factor-clock"; > clocks = <&rpmhcc RPMH_CXO_CLK_A>; > clock-mult = <1>; > clock-div = <2>; > }; > }; Does this snippet pass bindings validation? > > The clock nodes will be probed on of_clk_init. Ah, I see. of_clk_init() will initialize clocks even if the parent device is not fully probed. Thank you for the explanation!
On Wed, Jan 04, 2023 at 02:45:04PM +0200, Abel Vesa wrote: > On 23-01-04 12:46:55, Dmitry Baryshkov wrote: > > On 04/01/2023 11:34, Abel Vesa wrote: > > > Adds the RPMH clocks present in SM8550 SoC. > > > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > > --- > > > drivers/clk/qcom/clk-rpmh.c | 36 ++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 36 insertions(+) > > > > I think the plan was to have the _PAD clock as a child node of the rpmcc. Is > > it still the planned implementation? > > Yes. Here is how the dts rpmhcc node will look like: > > rpmhcc: clock-controller { > compatible = "qcom,sm8550-rpmh-clk"; > #clock-cells = <1>; > clock-names = "xo"; > clocks = <&xo_board>; > > bi_tcxo_div2: bi-tcxo-div2-clk { Considering that the remainder of the clock exposed (except ipa clock) by the rpmhcc provider represent clock signals coming out of the pmic; and that this divider is not located in the aoss (rsc), I don't think these nodes should live here. /clocks seems perfectly fine to me. Regards, Bjorn > #clock-cells = <0>; > compatible = "fixed-factor-clock"; > clocks = <&rpmhcc RPMH_CXO_CLK>; > clock-mult = <1>; > clock-div = <2>; > }; > > bi_tcxo_ao_div2: bi-tcxo-div2-ao-clk { > #clock-cells = <0>; > compatible = "fixed-factor-clock"; > clocks = <&rpmhcc RPMH_CXO_CLK_A>; > clock-mult = <1>; > clock-div = <2>; > }; > }; > > The clock nodes will be probed on of_clk_init. > > > > > -- > > With best wishes > > Dmitry > >
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 586a810c682c..7db5a53d73f0 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -366,6 +366,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); +DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); +DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); + +DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); +DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); +DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); + DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); DEFINE_CLK_RPMH_BCM(ce, "CE0"); @@ -576,6 +586,31 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), }; +static struct clk_hw *sm8550_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8550 = { + .clks = sm8550_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), +}; + static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, @@ -742,6 +777,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, + { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, { } };