| Message ID | 20230109174511.1740856-1-brgl@bgdev.pl (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: qcom: add support for sa8775p-ride | expand |
On 9.01.2023 18:44, Bartosz Golaszewski wrote: > From: Shazad Hussain <quic_shazhuss@quicinc.com> > > Add support for the Global Clock Controller found in the QTI SA8775P > platforms. > > Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > [Bartosz: made the driver ready for upstream] > Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- [...] > + > +static struct gdsc usb20_prim_gdsc = { > + .gdscr = 0x1C004, Please use lowercase hex literals outside #defines. > + .pd = { > + .name = "usb20_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + [...] > + > +static const struct regmap_config gcc_sa8775p_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x472cffc, This is faaaaar more than what your DT node specifies. With these two fixed, LGTM: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc gcc_sa8775p_desc = { > + .config = &gcc_sa8775p_regmap_config, > + .clks = gcc_sa8775p_clocks, > + .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks), > + .resets = gcc_sa8775p_resets, > + .num_resets = ARRAY_SIZE(gcc_sa8775p_resets), > + .gdscs = gcc_sa8775p_gdscs, > + .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs), > +}; > + > +static const struct of_device_id gcc_sa8775p_match_table[] = { > + { .compatible = "qcom,gcc-sa8775p" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); > + > +static int gcc_sa8775p_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, > + ARRAY_SIZE(gcc_dfs_clocks)); > + if (ret) > + return ret; > + > + /* > + * Keep the clocks always-ON > + * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, > + * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, > + * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. > + */ > + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); > + regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); > + > + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); > +} > + > +static struct platform_driver gcc_sa8775p_driver = { > + .probe = gcc_sa8775p_probe, > + .driver = { > + .name = "gcc-sa8775p", > + .of_match_table = gcc_sa8775p_match_table, > + }, > +}; > + > +static int __init gcc_sa8775p_init(void) > +{ > + return platform_driver_register(&gcc_sa8775p_driver); > +} > +subsys_initcall(gcc_sa8775p_init); > + > +static void __exit gcc_sa8775p_exit(void) > +{ > + platform_driver_unregister(&gcc_sa8775p_driver); > +} > +module_exit(gcc_sa8775p_exit); > + > +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); > +MODULE_LICENSE("GPL");
On 9.01.2023 18:58, Konrad Dybcio wrote: > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: >> From: Shazad Hussain <quic_shazhuss@quicinc.com> >> >> Add support for the Global Clock Controller found in the QTI SA8775P >> platforms. >> >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> >> [Bartosz: made the driver ready for upstream] >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> --- > [...] > >> + >> +static struct gdsc usb20_prim_gdsc = { >> + .gdscr = 0x1C004, > Please use lowercase hex literals outside #defines. > >> + .pd = { >> + .name = "usb20_prim_gdsc", >> + }, >> + .pwrsts = PWRSTS_OFF_ON, >> +}; >> + > [...] > >> + >> +static const struct regmap_config gcc_sa8775p_regmap_config = { >> + .reg_bits = 32, >> + .reg_stride = 4, >> + .val_bits = 32, >> + .max_register = 0x472cffc, > This is faaaaar more than what your DT node specifies. > > With these two fixed, LGTM: > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Konrad >> + .fast_io = true, >> +}; >> + >> +static const struct qcom_cc_desc gcc_sa8775p_desc = { >> + .config = &gcc_sa8775p_regmap_config, >> + .clks = gcc_sa8775p_clocks, >> + .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks), >> + .resets = gcc_sa8775p_resets, >> + .num_resets = ARRAY_SIZE(gcc_sa8775p_resets), >> + .gdscs = gcc_sa8775p_gdscs, >> + .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs), >> +}; >> + >> +static const struct of_device_id gcc_sa8775p_match_table[] = { >> + { .compatible = "qcom,gcc-sa8775p" }, One more thing, this should be qcom,sa8775p-gcc. Konrad >> + { } >> +}; >> +MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); >> + >> +static int gcc_sa8775p_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; >> + int ret; >> + >> + regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc); >> + if (IS_ERR(regmap)) >> + return PTR_ERR(regmap); >> + >> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, >> + ARRAY_SIZE(gcc_dfs_clocks)); >> + if (ret) >> + return ret; >> + >> + /* >> + * Keep the clocks always-ON >> + * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, >> + * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, >> + * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. >> + */ >> + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); >> + >> + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); >> +} >> + >> +static struct platform_driver gcc_sa8775p_driver = { >> + .probe = gcc_sa8775p_probe, >> + .driver = { >> + .name = "gcc-sa8775p", >> + .of_match_table = gcc_sa8775p_match_table, >> + }, >> +}; >> + >> +static int __init gcc_sa8775p_init(void) >> +{ >> + return platform_driver_register(&gcc_sa8775p_driver); >> +} >> +subsys_initcall(gcc_sa8775p_init); >> + >> +static void __exit gcc_sa8775p_exit(void) >> +{ >> + platform_driver_unregister(&gcc_sa8775p_driver); >> +} >> +module_exit(gcc_sa8775p_exit); >> + >> +MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); >> +MODULE_LICENSE("GPL");
On 09/01/2023 19:44, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and its reference > board: sa8775p-ride. The dtsi contains basic SoC description required for > a simple boot-to-shell. The dts enables boot-to-shell with UART on the > sa8775p-ride board. There are three new drivers required to boot the board: > pinctrl, interconnect and GCC clock. Other patches contain various tweaks > to existing code. More support is coming up. > > Bartosz Golaszewski (15): > dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p > arm64: defconfig: enable the clock driver for Qualcomm SA8775P > platforms > dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p > clk: qcom: rpmh: add clocks for sa8775p > dt-bindings: interconnect: qcom: document the interconnects for > sa8775p > arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P > dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm > arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P > platforms > dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform > dt-bindings: power: qcom,rpmpd: document sa8775p > soc: qcom: rmphpd: add power domains for sa8775p > dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P > iommu: arm-smmu: qcom: add support for sa8775p > dt-bindings: arm: qcom: document the sa8775p reference board > arm64: dts: qcom: add initial support for qcom sa8775p-ride > > Shazad Hussain (2): > clk: qcom: add the GCC driver for sa8775p This patch didn't make it to the list. Please check if you can fix or split it somehow?
On 9.01.2023 21:13, Dmitry Baryshkov wrote: > On 09/01/2023 19:44, Bartosz Golaszewski wrote: >> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> >> This adds basic support for the Qualcomm sa8775p platform and its reference >> board: sa8775p-ride. The dtsi contains basic SoC description required for >> a simple boot-to-shell. The dts enables boot-to-shell with UART on the >> sa8775p-ride board. There are three new drivers required to boot the board: >> pinctrl, interconnect and GCC clock. Other patches contain various tweaks >> to existing code. More support is coming up. >> >> Bartosz Golaszewski (15): >> dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p >> arm64: defconfig: enable the clock driver for Qualcomm SA8775P >> platforms >> dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p >> clk: qcom: rpmh: add clocks for sa8775p >> dt-bindings: interconnect: qcom: document the interconnects for >> sa8775p >> arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P >> dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm >> arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P >> platforms >> dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform >> dt-bindings: power: qcom,rpmpd: document sa8775p >> soc: qcom: rmphpd: add power domains for sa8775p >> dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P >> iommu: arm-smmu: qcom: add support for sa8775p >> dt-bindings: arm: qcom: document the sa8775p reference board >> arm64: dts: qcom: add initial support for qcom sa8775p-ride >> >> Shazad Hussain (2): >> clk: qcom: add the GCC driver for sa8775p > > This patch didn't make it to the list. Please check if you can fix or split it somehow? It's a known issue with lists clipping messages that are too long. I'll forward it to you. Konrad >
On 09/01/2023 22:59, Konrad Dybcio wrote: > > > On 9.01.2023 21:13, Dmitry Baryshkov wrote: >> On 09/01/2023 19:44, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >>> >>> This adds basic support for the Qualcomm sa8775p platform and its reference >>> board: sa8775p-ride. The dtsi contains basic SoC description required for >>> a simple boot-to-shell. The dts enables boot-to-shell with UART on the >>> sa8775p-ride board. There are three new drivers required to boot the board: >>> pinctrl, interconnect and GCC clock. Other patches contain various tweaks >>> to existing code. More support is coming up. >>> >>> Bartosz Golaszewski (15): >>> dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p >>> arm64: defconfig: enable the clock driver for Qualcomm SA8775P >>> platforms >>> dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p >>> clk: qcom: rpmh: add clocks for sa8775p >>> dt-bindings: interconnect: qcom: document the interconnects for >>> sa8775p >>> arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P >>> dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm >>> arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P >>> platforms >>> dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform >>> dt-bindings: power: qcom,rpmpd: document sa8775p >>> soc: qcom: rmphpd: add power domains for sa8775p >>> dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P >>> iommu: arm-smmu: qcom: add support for sa8775p >>> dt-bindings: arm: qcom: document the sa8775p reference board >>> arm64: dts: qcom: add initial support for qcom sa8775p-ride >>> >>> Shazad Hussain (2): >>> clk: qcom: add the GCC driver for sa8775p >> >> This patch didn't make it to the list. Please check if you can fix or split it somehow? > It's a known issue with lists clipping messages that are too long. > I'll forward it to you. Thank you!
On 09/01/2023 19:58, Konrad Dybcio wrote: > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: >> From: Shazad Hussain <quic_shazhuss@quicinc.com> >> >> Add support for the Global Clock Controller found in the QTI SA8775P >> platforms. >> >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> >> [Bartosz: made the driver ready for upstream] >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >> --- > [...] > As the driver didn't get to the list, I'll comment OOB. Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks).
On Mon, 9 Jan 2023 18:44:53 +0100, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and its reference > board: sa8775p-ride. The dtsi contains basic SoC description required for > a simple boot-to-shell. The dts enables boot-to-shell with UART on the > sa8775p-ride board. There are three new drivers required to boot the board: > pinctrl, interconnect and GCC clock. Other patches contain various tweaks > to existing code. More support is coming up. > > [...] Applied, thanks! [13/18] dt-bindings: power: qcom,rpmpd: document sa8775p commit: b4f0370d3ce276397f5c48af99d0b77548825eb1 [14/18] soc: qcom: rmphpd: add power domains for sa8775p commit: 91e910adc59a6954e475dd2d6a4534ac56dd8eed Best regards,
On Mon, Jan 9, 2023 at 10:06 PM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 09/01/2023 19:58, Konrad Dybcio wrote: > > > > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: > >> From: Shazad Hussain <quic_shazhuss@quicinc.com> > >> > >> Add support for the Global Clock Controller found in the QTI SA8775P > >> platforms. > >> > >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > >> [Bartosz: made the driver ready for upstream] > >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > >> --- > > [...] > > > > As the driver didn't get to the list, I'll comment OOB. > > Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks). > Looks like it's impossible for this platform as the PCIe PIPE clocks have two parents. Bart
On Tue, 17 Jan 2023 at 14:44, Bartosz Golaszewski <brgl@bgdev.pl> wrote: > > On Mon, Jan 9, 2023 at 10:06 PM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: > > > > On 09/01/2023 19:58, Konrad Dybcio wrote: > > > > > > > > > On 9.01.2023 18:44, Bartosz Golaszewski wrote: > > >> From: Shazad Hussain <quic_shazhuss@quicinc.com> > > >> > > >> Add support for the Global Clock Controller found in the QTI SA8775P > > >> platforms. > > >> > > >> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > > >> [Bartosz: made the driver ready for upstream] > > >> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > >> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > >> --- > > > [...] > > > > > > > As the driver didn't get to the list, I'll comment OOB. > > > > Please use clk_regmap_phy_mux_ops where applicable (PCIe PIPE clocks). > > > > Looks like it's impossible for this platform as the PCIe PIPE clocks > have two parents. That's the point, please check the history of other platforms. XO becomes the 'off' state rather than being a separate parent.
On Mon, 9 Jan 2023 18:44:53 +0100, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and its reference > board: sa8775p-ride. The dtsi contains basic SoC description required for > a simple boot-to-shell. The dts enables boot-to-shell with UART on the > sa8775p-ride board. There are three new drivers required to boot the board: > pinctrl, interconnect and GCC clock. Other patches contain various tweaks > to existing code. More support is coming up. > > [...] Applied, thanks! [03/18] arm64: defconfig: enable the clock driver for Qualcomm SA8775P platforms commit: 1a87f7e5fa10b23633da03aed6b7c7e716457304 Best regards,
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> This adds basic support for the Qualcomm sa8775p platform and its reference board: sa8775p-ride. The dtsi contains basic SoC description required for a simple boot-to-shell. The dts enables boot-to-shell with UART on the sa8775p-ride board. There are three new drivers required to boot the board: pinctrl, interconnect and GCC clock. Other patches contain various tweaks to existing code. More support is coming up. Bartosz Golaszewski (15): dt-bindings: clock: sa8775p: add bindings for Qualcomm gcc-sa8775p arm64: defconfig: enable the clock driver for Qualcomm SA8775P platforms dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775p clk: qcom: rpmh: add clocks for sa8775p dt-bindings: interconnect: qcom: document the interconnects for sa8775p arm64: defconfig: enable the interconnect driver for Qualcomm SA8775P dt-bindings: pinctrl: sa8775p: add bindings for qcom,sa8775p-tlmm arm64: defconfig: enable the pinctrl driver for Qualcomm SA8775P platforms dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform dt-bindings: power: qcom,rpmpd: document sa8775p soc: qcom: rmphpd: add power domains for sa8775p dt-bindings: arm-smmu: document the smmu on Qualcomm SA8775P iommu: arm-smmu: qcom: add support for sa8775p dt-bindings: arm: qcom: document the sa8775p reference board arm64: dts: qcom: add initial support for qcom sa8775p-ride Shazad Hussain (2): clk: qcom: add the GCC driver for sa8775p interconnect: qcom: add a driver for sa8775p Yadu MG (1): pinctrl: qcom: sa8775p: add the pinctrl driver for the sa8775p platform .../devicetree/bindings/arm/qcom.yaml | 5 + .../bindings/clock/qcom,gcc-sa8775p.yaml | 77 + .../bindings/clock/qcom,rpmhcc.yaml | 1 + .../bindings/interconnect/qcom,rpmh.yaml | 14 + .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + .../bindings/mailbox/qcom-ipcc.yaml | 1 + .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 142 + .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 39 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 841 +++ arch/arm64/configs/defconfig | 3 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 17 + drivers/clk/qcom/gcc-sa8775p.c | 4806 +++++++++++++++++ drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sa8775p.c | 2542 +++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1649 ++++++ drivers/soc/qcom/rpmhpd.c | 34 + include/dt-bindings/clock/qcom,gcc-sa8775p.h | 320 ++ .../dt-bindings/interconnect/qcom,sa8775p.h | 231 + include/dt-bindings/power/qcom-rpmpd.h | 19 + 27 files changed, 10776 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sa8775p.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi create mode 100644 drivers/clk/qcom/gcc-sa8775p.c create mode 100644 drivers/interconnect/qcom/sa8775p.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sa8775p.h create mode 100644 include/dt-bindings/interconnect/qcom,sa8775p.h