Message ID | 20230110113533.744436-1-tvrtko.ursulin@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v4] drm/i915: Do not cover all future platforms in TLB invalidation | expand |
On Tue, Jan 10, 2023 at 11:35:33AM +0000, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Revert to the original explicit approach and document the reasoning > behind it. > > v2: > * DG2 needs to be covered too. (Matt) > > v3: > * Full version check for Gen12 to avoid catching all future platforms. > (Matt) > > v4: > * Be totally explicit on the Gen12 branch. (Andrzej) > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> # v1 > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> # v3 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> for v4 as well. Matt > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 7eeee5a7cb33..5721bf85d119 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -1070,10 +1070,23 @@ static void mmio_invalidate_full(struct intel_gt *gt) > unsigned int num = 0; > unsigned long flags; > > - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { > + /* > + * New platforms should not be added with catch-all-newer (>=) > + * condition so that any later platform added triggers the below warning > + * and in turn mandates a human cross-check of whether the invalidation > + * flows have compatible semantics. > + * > + * For instance with the 11.00 -> 12.00 transition three out of five > + * respective engine registers were moved to masked type. Then after the > + * 12.00 -> 12.50 transition multi cast handling is required too. > + */ > + > + if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) || > + GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) { > regs = NULL; > num = ARRAY_SIZE(xehp_regs); > - } else if (GRAPHICS_VER(i915) == 12) { > + } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) || > + GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) { > regs = gen12_regs; > num = ARRAY_SIZE(gen12_regs); > } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { > -- > 2.34.1 >
On 10/01/2023 16:07, Matt Roper wrote: > On Tue, Jan 10, 2023 at 11:35:33AM +0000, Tvrtko Ursulin wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> Revert to the original explicit approach and document the reasoning >> behind it. >> >> v2: >> * DG2 needs to be covered too. (Matt) >> >> v3: >> * Full version check for Gen12 to avoid catching all future platforms. >> (Matt) >> >> v4: >> * Be totally explicit on the Gen12 branch. (Andrzej) >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Matt Roper <matthew.d.roper@intel.com> >> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> >> Cc: Andrzej Hajda <andrzej.hajda@intel.com> >> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> # v1 >> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> # v3 > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > for v4 as well. Thanks, pushed! So next I have that patch which moves the register/bits selection logic to engine init time. I will send it out rebased but do not intend to merge before the tlb invalidation selftest can land upstream. Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 7eeee5a7cb33..5721bf85d119 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1070,10 +1070,23 @@ static void mmio_invalidate_full(struct intel_gt *gt) unsigned int num = 0; unsigned long flags; - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { + /* + * New platforms should not be added with catch-all-newer (>=) + * condition so that any later platform added triggers the below warning + * and in turn mandates a human cross-check of whether the invalidation + * flows have compatible semantics. + * + * For instance with the 11.00 -> 12.00 transition three out of five + * respective engine registers were moved to masked type. Then after the + * 12.00 -> 12.50 transition multi cast handling is required too. + */ + + if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) || + GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) { regs = NULL; num = ARRAY_SIZE(xehp_regs); - } else if (GRAPHICS_VER(i915) == 12) { + } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) || + GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) { regs = gen12_regs; num = ARRAY_SIZE(gen12_regs); } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {