| Message ID | 20230111005642.300761-6-alan.previn.teres.alexis@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/pxp: Add MTL PXP Support | expand |
Hi Alan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on cc44a1e87ea6b788868878295119398966f98a81]
url: https://github.com/intel-lab-lkp/linux/commits/Alan-Previn/drm-i915-pxp-Add-MTL-PXP-GSC-CS-back-end-skeleton/20230111-085853
base: cc44a1e87ea6b788868878295119398966f98a81
patch link: https://lore.kernel.org/r/20230111005642.300761-6-alan.previn.teres.alexis%40intel.com
patch subject: [Intel-gfx] [PATCH 5/9] drm/i915/pxp: Add GSC-CS backend-teelink for send-message function
config: i386-allyesconfig
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/b3a566b139d02e25dd05bc553375402a97ecf9c0
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Alan-Previn/drm-i915-pxp-Add-MTL-PXP-GSC-CS-back-end-skeleton/20230111-085853
git checkout b3a566b139d02e25dd05bc553375402a97ecf9c0
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 olddefconfig
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from include/linux/device.h:15,
from include/linux/node.h:18,
from include/linux/cpu.h:17,
from include/linux/static_call.h:135,
from arch/x86/include/asm/perf_event.h:5,
from include/linux/perf_event.h:25,
from drivers/gpu/drm/i915/i915_pmu.h:11,
from drivers/gpu/drm/i915/gt/intel_engine_types.h:21,
from drivers/gpu/drm/i915/gt/intel_context_types.h:18,
from drivers/gpu/drm/i915/gem/i915_gem_context_types.h:20,
from drivers/gpu/drm/i915/i915_request.h:34,
from drivers/gpu/drm/i915/i915_active.h:13,
from drivers/gpu/drm/i915/gt/intel_context.h:13,
from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:8:
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c: In function 'gsccs_send_message':
>> include/drm/drm_print.h:456:39: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
456 | dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
| ^~~~~~~~
include/linux/dev_printk.h:110:30: note: in definition of macro 'dev_printk_index_wrap'
110 | _p_func(dev, fmt, ##__VA_ARGS__); \
| ^~~
include/linux/dev_printk.h:146:61: note: in expansion of macro 'dev_fmt'
146 | dev_printk_index_wrap(_dev_warn, KERN_WARNING, dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
include/drm/drm_print.h:456:9: note: in expansion of macro 'dev_warn'
456 | dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
| ^~~~
include/drm/drm_print.h:466:9: note: in expansion of macro '__drm_printk'
466 | __drm_printk((drm), warn,, fmt, ##__VA_ARGS__)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:116:17: note: in expansion of macro 'drm_warn'
116 | drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n",
| ^~~~~~~~
In file included from include/drm/ttm/ttm_resource.h:34,
from include/drm/ttm/ttm_device.h:30,
from drivers/gpu/drm/i915/i915_drv.h:37,
from drivers/gpu/drm/i915/gt/intel_context.h:14,
from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:8:
>> drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:120:37: error: format '%ld' expects argument of type 'long int', but argument 6 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
120 | drm_dbg(&i915->drm, "caller unexpected PXP reply size %u (%ld)\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
121 | reply_size, msg_out_size_max);
| ~~~~~~~~~~~~~~~~
| |
| size_t {aka unsigned int}
include/drm/drm_print.h:410:39: note: in definition of macro 'drm_dev_dbg'
410 | __drm_dev_dbg(NULL, dev, cat, fmt, ##__VA_ARGS__)
| ^~~
include/drm/drm_print.h:510:33: note: in expansion of macro 'drm_dbg_driver'
510 | #define drm_dbg(drm, fmt, ...) drm_dbg_driver(drm, fmt, ##__VA_ARGS__)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:120:17: note: in expansion of macro 'drm_dbg'
120 | drm_dbg(&i915->drm, "caller unexpected PXP reply size %u (%ld)\n",
| ^~~~~~~
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:120:77: note: format string is defined here
120 | drm_dbg(&i915->drm, "caller unexpected PXP reply size %u (%ld)\n",
| ~~^
| |
| long int
| %d
At top level:
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:43:12: error: 'gsccs_send_message' defined but not used [-Werror=unused-function]
43 | static int gsccs_send_message(struct intel_pxp *pxp,
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +120 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
42
43 static int gsccs_send_message(struct intel_pxp *pxp,
44 void *msg_in, size_t msg_in_size,
45 void *msg_out, size_t msg_out_size_max,
46 size_t *msg_out_len)
47 {
48 struct intel_gt *gt = pxp->ctrl_gt;
49 struct drm_i915_private *i915 = gt->i915;
50 struct gsccs_session_resources *exec = &pxp_to_gsccs_priv(pxp)->arb_exec_res;
51 struct intel_gsc_mtl_header *header = exec->pkt_vaddr;
52 struct intel_gsc_heci_non_priv_pkt pkt;
53 size_t max_msg_size;
54 u32 reply_size;
55 int ret;
56
57 if (!intel_uc_uses_gsc_uc(>->uc))
58 return -ENODEV;
59
60 if (!exec->ce)
61 return -ENODEV;
62
63 max_msg_size = PXP43_MAX_HECI_IN_SIZE - sizeof(*header);
64
65 if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size)
66 return -ENOSPC;
67
68 mutex_lock(&exec->cmd_mutex);
69
70 if (!exec->pkt_vma || !exec->bb_vma)
71 return -ENOENT;
72
73 memset(header, 0, sizeof(*header));
74 intel_gsc_uc_heci_cmd_emit_mtl_header(header, MTL_HECI_CLIENT_PXP, msg_in_size,
75 exec->host_session_handle, 0);
76
77 memcpy(exec->pkt_vaddr + sizeof(*header), msg_in, msg_in_size);
78
79 pkt.addr_in = i915_vma_offset(exec->pkt_vma);
80 pkt.size_in = header->message_size;
81 pkt.addr_out = pkt.addr_in + PXP43_MAX_HECI_IN_SIZE;
82 pkt.size_out = msg_out_size_max + sizeof(*header);
83 pkt.heci_pkt_vma = exec->pkt_vma;
84 pkt.bb_vma = exec->bb_vma;
85
86 ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&pxp->ctrl_gt->uc.gsc,
87 exec->ce, &pkt, exec->bb_vaddr, 500);
88 if (ret) {
89 drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret);
90 goto unlock;
91 }
92
93 /* we keep separate location for reply, so get the response header loc first */
94 header = exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE;
95
96 /* Response validity marker, status and busyness */
97 if (header->validity_marker != MTL_HECI_VALIDITY_MARKER) {
98 drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n");
99 ret = -EINVAL;
100 goto unlock;
101 }
102 if (header->status != 0) {
103 drm_dbg(&i915->drm, "gsc PXP reply status has error = 0x%08x\n",
104 header->status);
105 ret = -EINVAL;
106 goto unlock;
107 }
108 if (header->flags & MTL_GSC_HDR_FLAG_MSG_PENDING) {
109 drm_dbg(&i915->drm, "gsc PXP reply is busy\n");
110 ret = -EAGAIN;
111 goto unlock;
112 }
113
114 reply_size = header->message_size - sizeof(*header);
115 if (reply_size > msg_out_size_max) {
> 116 drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n",
117 reply_size, msg_out_size_max);
118 reply_size = msg_out_size_max;
119 } else if (reply_size != msg_out_size_max) {
> 120 drm_dbg(&i915->drm, "caller unexpected PXP reply size %u (%ld)\n",
121 reply_size, msg_out_size_max);
122 }
123
124 memcpy(msg_out, exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE + sizeof(*header),
125 reply_size);
126 if (msg_out_len)
127 *msg_out_len = reply_size;
128
129 unlock:
130 mutex_unlock(&exec->cmd_mutex);
131 return ret;
132 }
133
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c index 97ca187e6fde..84045e18591e 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c @@ -6,6 +6,7 @@ #include "gem/i915_gem_internal.h" #include "gt/intel_context.h" +#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h" #include "i915_drv.h" #include "intel_pxp_cmd_interface_43.h" @@ -39,6 +40,97 @@ static inline struct gsccs_teelink_priv *pxp_to_gsccs_priv(struct intel_pxp *pxp return (struct gsccs_teelink_priv *)pxp->gsccs_priv; } +static int gsccs_send_message(struct intel_pxp *pxp, + void *msg_in, size_t msg_in_size, + void *msg_out, size_t msg_out_size_max, + size_t *msg_out_len) +{ + struct intel_gt *gt = pxp->ctrl_gt; + struct drm_i915_private *i915 = gt->i915; + struct gsccs_session_resources *exec = &pxp_to_gsccs_priv(pxp)->arb_exec_res; + struct intel_gsc_mtl_header *header = exec->pkt_vaddr; + struct intel_gsc_heci_non_priv_pkt pkt; + size_t max_msg_size; + u32 reply_size; + int ret; + + if (!intel_uc_uses_gsc_uc(>->uc)) + return -ENODEV; + + if (!exec->ce) + return -ENODEV; + + max_msg_size = PXP43_MAX_HECI_IN_SIZE - sizeof(*header); + + if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size) + return -ENOSPC; + + mutex_lock(&exec->cmd_mutex); + + if (!exec->pkt_vma || !exec->bb_vma) + return -ENOENT; + + memset(header, 0, sizeof(*header)); + intel_gsc_uc_heci_cmd_emit_mtl_header(header, MTL_HECI_CLIENT_PXP, msg_in_size, + exec->host_session_handle, 0); + + memcpy(exec->pkt_vaddr + sizeof(*header), msg_in, msg_in_size); + + pkt.addr_in = i915_vma_offset(exec->pkt_vma); + pkt.size_in = header->message_size; + pkt.addr_out = pkt.addr_in + PXP43_MAX_HECI_IN_SIZE; + pkt.size_out = msg_out_size_max + sizeof(*header); + pkt.heci_pkt_vma = exec->pkt_vma; + pkt.bb_vma = exec->bb_vma; + + ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&pxp->ctrl_gt->uc.gsc, + exec->ce, &pkt, exec->bb_vaddr, 500); + if (ret) { + drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret); + goto unlock; + } + + /* we keep separate location for reply, so get the response header loc first */ + header = exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE; + + /* Response validity marker, status and busyness */ + if (header->validity_marker != MTL_HECI_VALIDITY_MARKER) { + drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n"); + ret = -EINVAL; + goto unlock; + } + if (header->status != 0) { + drm_dbg(&i915->drm, "gsc PXP reply status has error = 0x%08x\n", + header->status); + ret = -EINVAL; + goto unlock; + } + if (header->flags & MTL_GSC_HDR_FLAG_MSG_PENDING) { + drm_dbg(&i915->drm, "gsc PXP reply is busy\n"); + ret = -EAGAIN; + goto unlock; + } + + reply_size = header->message_size - sizeof(*header); + if (reply_size > msg_out_size_max) { + drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n", + reply_size, msg_out_size_max); + reply_size = msg_out_size_max; + } else if (reply_size != msg_out_size_max) { + drm_dbg(&i915->drm, "caller unexpected PXP reply size %u (%ld)\n", + reply_size, msg_out_size_max); + } + + memcpy(msg_out, exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE + sizeof(*header), + reply_size); + if (msg_out_len) + *msg_out_len = reply_size; + +unlock: + mutex_unlock(&exec->cmd_mutex); + return ret; +} + int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id) {
Populate the backend-teelink abstraction layer using GSC-CS engine for MTL (and future) products. The PXP backend for sending messages Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+)