| Message ID | 20230118193518.26433-1-farosas@suse.de (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/arm: CONFIG_TCG=n part 1 | expand |
Hi Fabiano, On 18/1/23 20:34, Fabiano Rosas wrote: > These are the already reviewed patches from the first half of my > previous series: > https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de > > This unbreaks the --disable-tcg build, but there are issues in runtime > that are still being hashed out in the other series. > > For the build _with_ TCG, this should behave the same as master. > > Based on Richard's "target/arm: Introduce aarch64_set_svcr": > https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org $ git am 20230111_richard_henderson_target_arm_introduce_aarch64_set_svcr.mbx Applying: target/arm: Introduce aarch64_set_svcr $ git am ./20230118_farosas_target_arm_config_tcg_n_part_1.mbx Applying: target/arm: rename handle_semihosting to tcg_handle_semihosting Applying: target/arm: wrap psci call with tcg_enabled Applying: target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Applying: target/arm: Move PC alignment check Applying: target/arm: Move cpregs code out of cpu.h Applying: target/arm: Move define_debug_regs() to cpregs.c error: target/arm/cpregs.c: does not exist in index Patch failed at 0006 target/arm: Move define_debug_regs() to cpregs.c I am based on commit 7ec8aeb604 ("Merge tag 'pull-tpm-2023-01-17-1' of https://github.com/stefanberger/qemu-tpm into staging"), what am I missing?
Philippe Mathieu-Daudé <philmd@linaro.org> writes: > Hi Fabiano, > > On 18/1/23 20:34, Fabiano Rosas wrote: >> These are the already reviewed patches from the first half of my >> previous series: >> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >> >> This unbreaks the --disable-tcg build, but there are issues in runtime >> that are still being hashed out in the other series. >> >> For the build _with_ TCG, this should behave the same as master. >> >> Based on Richard's "target/arm: Introduce aarch64_set_svcr": >> https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org > > $ git am > 20230111_richard_henderson_target_arm_introduce_aarch64_set_svcr.mbx > Applying: target/arm: Introduce aarch64_set_svcr > $ git am ./20230118_farosas_target_arm_config_tcg_n_part_1.mbx > Applying: target/arm: rename handle_semihosting to tcg_handle_semihosting > Applying: target/arm: wrap psci call with tcg_enabled > Applying: target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() > Applying: target/arm: Move PC alignment check > Applying: target/arm: Move cpregs code out of cpu.h > Applying: target/arm: Move define_debug_regs() to cpregs.c > error: target/arm/cpregs.c: does not exist in index > Patch failed at 0006 target/arm: Move define_debug_regs() to cpregs.c > > I am based on commit 7ec8aeb604 ("Merge tag 'pull-tpm-2023-01-17-1' of > https://github.com/stefanberger/qemu-tpm into staging"), what am I missing? How did you fetch the series? You are missing patch 06. Maybe it is too big for the method you used?
On 18/1/23 22:28, Fabiano Rosas wrote: > Philippe Mathieu-Daudé <philmd@linaro.org> writes: > >> Hi Fabiano, >> >> On 18/1/23 20:34, Fabiano Rosas wrote: >>> These are the already reviewed patches from the first half of my >>> previous series: >>> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >>> >>> This unbreaks the --disable-tcg build, but there are issues in runtime >>> that are still being hashed out in the other series. >>> >>> For the build _with_ TCG, this should behave the same as master. >>> >>> Based on Richard's "target/arm: Introduce aarch64_set_svcr": >>> https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org >> >> $ git am >> 20230111_richard_henderson_target_arm_introduce_aarch64_set_svcr.mbx >> Applying: target/arm: Introduce aarch64_set_svcr >> $ git am ./20230118_farosas_target_arm_config_tcg_n_part_1.mbx >> Applying: target/arm: rename handle_semihosting to tcg_handle_semihosting >> Applying: target/arm: wrap psci call with tcg_enabled >> Applying: target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() >> Applying: target/arm: Move PC alignment check >> Applying: target/arm: Move cpregs code out of cpu.h >> Applying: target/arm: Move define_debug_regs() to cpregs.c >> error: target/arm/cpregs.c: does not exist in index >> Patch failed at 0006 target/arm: Move define_debug_regs() to cpregs.c >> >> I am based on commit 7ec8aeb604 ("Merge tag 'pull-tpm-2023-01-17-1' of >> https://github.com/stefanberger/qemu-tpm into staging"), what am I missing? > > How did you fetch the series? You are missing patch 06. Maybe it is too > big for the method you used? Actually the tool warned about patch 6 missing, but I didn't notice: $ b4 am 20230118193518.26433-1-farosas@suse.de Grabbing thread from lore.kernel.org/all/20230118193518.26433-1-farosas%40suse.de/t.mbox.gz Analyzing 20 messages in the thread Checking attestation on all messages, may take a moment... --- ✓ [PATCH 1/20] target/arm: rename handle_semihosting to tcg_handle_semihosting ✓ Signed: DKIM/suse.de ✓ [PATCH 2/20] target/arm: wrap psci call with tcg_enabled ✓ Signed: DKIM/suse.de ✓ [PATCH 3/20] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() ✓ Signed: DKIM/suse.de ✓ [PATCH 4/20] target/arm: Move PC alignment check ✓ Signed: DKIM/suse.de ✓ [PATCH 5/20] target/arm: Move cpregs code out of cpu.h ✓ Signed: DKIM/suse.de ERROR: missing [6/20]! ✓ [PATCH 7/20] target/arm: Move define_debug_regs() to cpregs.c ✓ Signed: DKIM/suse.de ✓ [PATCH 8/20] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled ✓ Signed: DKIM/suse.de ✓ [PATCH 9/20] target/arm: move translate modules to tcg/ ✓ Signed: DKIM/suse.de ✓ [PATCH 10/20] target/arm: move helpers to tcg/ ✓ Signed: DKIM/suse.de ✓ [PATCH 11/20] target/arm: Move psci.c into the tcg directory ✓ Signed: DKIM/suse.de ✓ [PATCH 12/20] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled ✓ Signed: DKIM/suse.de ✓ [PATCH 13/20] target/arm: Move hflags code into the tcg directory ✓ Signed: DKIM/suse.de ✓ [PATCH 14/20] target/arm: Move regime_using_lpae_format into internal.h ✓ Signed: DKIM/suse.de ✓ [PATCH 15/20] target/arm: Don't access TCG code when debugging with KVM ✓ Signed: DKIM/suse.de ✓ [PATCH 16/20] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code ✓ Signed: DKIM/suse.de ✓ [PATCH 17/20] target/arm: Move cortex sysregs into cpregs.c ✓ Signed: DKIM/suse.de ✓ [PATCH 18/20] tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI ✓ Signed: DKIM/suse.de ✓ [PATCH 19/20] tests/avocado: Skip tests that require a missing accelerator ✓ Signed: DKIM/suse.de ✓ [PATCH 20/20] tests/avocado: Tag TCG tests with accel:tcg ✓ Signed: DKIM/suse.de --- Total patches: 19 --- WARNING: Thread incomplete! Indeed patch 6 is missing: https://lore.kernel.org/qemu-devel/20230118193518.26433-1-farosas@suse.de/
On 19/1/23 08:05, Philippe Mathieu-Daudé wrote: > On 18/1/23 22:28, Fabiano Rosas wrote: >> Philippe Mathieu-Daudé <philmd@linaro.org> writes: >>> On 18/1/23 20:34, Fabiano Rosas wrote: >>>> These are the already reviewed patches from the first half of my >>>> previous series: >>>> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >>>> >>>> This unbreaks the --disable-tcg build, but there are issues in runtime >>>> that are still being hashed out in the other series. >>>> >>>> For the build _with_ TCG, this should behave the same as master. >>>> >>>> Based on Richard's "target/arm: Introduce aarch64_set_svcr": >>>> https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org >>> >>> $ git am >>> 20230111_richard_henderson_target_arm_introduce_aarch64_set_svcr.mbx >>> Applying: target/arm: Introduce aarch64_set_svcr >>> $ git am ./20230118_farosas_target_arm_config_tcg_n_part_1.mbx >>> Applying: target/arm: rename handle_semihosting to >>> tcg_handle_semihosting >>> Applying: target/arm: wrap psci call with tcg_enabled >>> Applying: target/arm: wrap call to aarch64_sve_change_el in >>> tcg_enabled() >>> Applying: target/arm: Move PC alignment check >>> Applying: target/arm: Move cpregs code out of cpu.h >>> Applying: target/arm: Move define_debug_regs() to cpregs.c >>> error: target/arm/cpregs.c: does not exist in index >>> Patch failed at 0006 target/arm: Move define_debug_regs() to cpregs.c >>> >>> I am based on commit 7ec8aeb604 ("Merge tag 'pull-tpm-2023-01-17-1' of >>> https://github.com/stefanberger/qemu-tpm into staging"), what am I >>> missing? >> >> How did you fetch the series? You are missing patch 06. Maybe it is too >> big for the method you used? > > Actually the tool warned about patch 6 missing, but I didn't notice: > > $ b4 am 20230118193518.26433-1-farosas@suse.de > Grabbing thread from > lore.kernel.org/all/20230118193518.26433-1-farosas%40suse.de/t.mbox.gz > Analyzing 20 messages in the thread > Checking attestation on all messages, may take a moment... > --- ... > ✓ [PATCH 5/20] target/arm: Move cpregs code out of cpu.h > ✓ Signed: DKIM/suse.de > ERROR: missing [6/20]! > ✓ [PATCH 7/20] target/arm: Move define_debug_regs() to cpregs.c > ✓ Signed: DKIM/suse.de ... > --- > Total patches: 19 > --- > WARNING: Thread incomplete! > > Indeed patch 6 is missing: > https://lore.kernel.org/qemu-devel/20230118193518.26433-1-farosas@suse.de/ I could find it here: https://marc.info/?l=qemu-arm&m=167407090423121
On 18/1/23 20:34, Fabiano Rosas wrote: > These are the already reviewed patches from the first half of my > previous series: > https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de > > This unbreaks the --disable-tcg build, but there are issues in runtime > that are still being hashed out in the other series. > > For the build _with_ TCG, this should behave the same as master. > > Based on Richard's "target/arm: Introduce aarch64_set_svcr": > https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org > > Claudio Fontana (5): > target/arm: rename handle_semihosting to tcg_handle_semihosting > target/arm: wrap psci call with tcg_enabled > target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() > target/arm: move helpers to tcg/ > target/arm: Move psci.c into the tcg directory > > Fabiano Rosas (15): > target/arm: Move PC alignment check > target/arm: Move cpregs code out of cpu.h > target/arm: Move cpregs code into cpregs.c > target/arm: Move define_debug_regs() to cpregs.c > target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled > target/arm: move translate modules to tcg/ > target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled > target/arm: Move hflags code into the tcg directory > target/arm: Move regime_using_lpae_format into internal.h > target/arm: Don't access TCG code when debugging with KVM > cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code > target/arm: Move cortex sysregs into cpregs.c > tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI > tests/avocado: Skip tests that require a missing accelerator > tests/avocado: Tag TCG tests with accel:tcg Testing on Darwin: 14/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/test-hmp ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code should not be reached 17/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/qom-test qemu-system-aarch64: unknown type 'arm-gicv3' 18/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/boot-serial-test qemu-system-aarch64: -accel tcg: invalid accelerator tcg 19/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/vnc-display-test qemu-system-aarch64: No machine specified, and there is no default 20/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/migration-test qemu-system-aarch64: -accel tcg: invalid accelerator tcg Reproducers: $ ./qemu-system-aarch64 -display none -S -M mps3-an547 -accel qtest -monitor stdio QEMU 7.2.50 monitor - type 'help' for more information (qemu) gva2gpa 0 ** ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code should not be reached Bail out! ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code should not be reached Abort trap: 6 frame #4: 0x0000000101fdd6cc libglib-2.0.0.dylib`g_assertion_message_expr + 116 frame #5: 0x0000000100360ce0 qemu-system-aarch64`arm_v7m_mmu_idx_for_secstate(env=<unavailable>, secstate=<unavailable>) at helper.c:2495:5 frame #6: 0x000000010035f7f4 qemu-system-aarch64`arm_mmu_idx_el(env=<unavailable>, el=<unavailable>) at helper.c:2514:16 frame #7: 0x00000001002d17ec qemu-system-aarch64`arm_cpu_get_phys_page_attrs_debug(cs=<unavailable>, addr=0, attrs=0x000000016fdfda50) at ptw.c:2982:23 frame #8: 0x00000001003c660c qemu-system-aarch64`hmp_gva2gpa(mon=0x000060000390f0c0, qdict=<unavailable>) at misc.c:714:12 $ ./qemu-system-aarch64 -display none -machine sbsa-ref -accel qtest qemu-system-aarch64: unknown type 'arm-gicv3' Abort trap: 6 frame #2: 0x00000001958522c8 libsystem_c.dylib`abort + 180 frame #3: 0x00000001003d32e8 qemu-system-aarch64`qdev_new(name="arm-gicv3") at qdev.c:164:9 frame #4: 0x00000001002f30d4 qemu-system-aarch64`sbsa_ref_init [inlined] create_gic(sms=0x0000000103ff0d10) at sbsa-ref.c:405:16 frame #5: 0x00000001002f30a0 qemu-system-aarch64`sbsa_ref_init(machine=0x0000000103ff0d10) at sbsa-ref.c:773:5 frame #6: 0x00000001000905c0 qemu-system-aarch64`machine_run_board_init(machine=0x0000000103ff0d10, mem_path=<unavailable>, errp=<unavailable>) at machine.c:1404:5
On 19/1/23 08:41, Philippe Mathieu-Daudé wrote: > On 18/1/23 20:34, Fabiano Rosas wrote: >> These are the already reviewed patches from the first half of my >> previous series: >> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >> >> This unbreaks the --disable-tcg build, but there are issues in runtime >> that are still being hashed out in the other series. >> >> For the build _with_ TCG, this should behave the same as master. >> >> Based on Richard's "target/arm: Introduce aarch64_set_svcr": >> https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org > Testing on Darwin: > > 18/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/boot-serial-test > qemu-system-aarch64: -accel tcg: invalid accelerator tcg > 20/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/migration-test > qemu-system-aarch64: -accel tcg: invalid accelerator tcg These two errors have been fixed by: https://lore.kernel.org/qemu-devel/20230119100537.5114-1-philmd@linaro.org/
On 19/1/23 08:41, Philippe Mathieu-Daudé wrote: > On 18/1/23 20:34, Fabiano Rosas wrote: >> These are the already reviewed patches from the first half of my >> previous series: >> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >> >> This unbreaks the --disable-tcg build, but there are issues in runtime >> that are still being hashed out in the other series. > Testing on Darwin: > 19/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/vnc-display-test > qemu-system-aarch64: No machine specified, and there is no default This one is fixed by: https://lore.kernel.org/qemu-devel/20230119120514.28778-3-philmd@linaro.org/
On 19/1/23 08:41, Philippe Mathieu-Daudé wrote: > On 18/1/23 20:34, Fabiano Rosas wrote: >> These are the already reviewed patches from the first half of my >> previous series: >> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >> >> This unbreaks the --disable-tcg build, but there are issues in runtime >> that are still being hashed out in the other series. >> >> For the build _with_ TCG, this should behave the same as master. > Testing on Darwin: > 17/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/qom-test > qemu-system-aarch64: unknown type 'arm-gicv3' > Reproducers: > $ ./qemu-system-aarch64 -display none -machine sbsa-ref -accel qtest > qemu-system-aarch64: unknown type 'arm-gicv3' > Abort trap: 6 > > frame #2: 0x00000001958522c8 libsystem_c.dylib`abort + 180 > frame #3: 0x00000001003d32e8 > qemu-system-aarch64`qdev_new(name="arm-gicv3") at qdev.c:164:9 > frame #4: 0x00000001002f30d4 qemu-system-aarch64`sbsa_ref_init > [inlined] create_gic(sms=0x0000000103ff0d10) at sbsa-ref.c:405:16 > frame #5: 0x00000001002f30a0 > qemu-system-aarch64`sbsa_ref_init(machine=0x0000000103ff0d10) at > sbsa-ref.c:773:5 > frame #6: 0x00000001000905c0 > qemu-system-aarch64`machine_run_board_init(machine=0x0000000103ff0d10, > mem_path=<unavailable>, errp=<unavailable>) at machine.c:1404:5 For this one, I *think* the sbsa-ref create_gic() should follow what the virt machine does to select the gic, generalizing Alex's changes from https://lore.kernel.org/qemu-devel/20221223090107.98888-1-agraf@csgraf.de/
Philippe Mathieu-Daudé <philmd@linaro.org> writes: > On 18/1/23 20:34, Fabiano Rosas wrote: >> These are the already reviewed patches from the first half of my >> previous series: >> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >> >> This unbreaks the --disable-tcg build, but there are issues in runtime >> that are still being hashed out in the other series. >> >> For the build _with_ TCG, this should behave the same as master. >> >> Based on Richard's "target/arm: Introduce aarch64_set_svcr": >> https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org >> >> Claudio Fontana (5): >> target/arm: rename handle_semihosting to tcg_handle_semihosting >> target/arm: wrap psci call with tcg_enabled >> target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() >> target/arm: move helpers to tcg/ >> target/arm: Move psci.c into the tcg directory >> >> Fabiano Rosas (15): >> target/arm: Move PC alignment check >> target/arm: Move cpregs code out of cpu.h >> target/arm: Move cpregs code into cpregs.c >> target/arm: Move define_debug_regs() to cpregs.c >> target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled >> target/arm: move translate modules to tcg/ >> target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled >> target/arm: Move hflags code into the tcg directory >> target/arm: Move regime_using_lpae_format into internal.h >> target/arm: Don't access TCG code when debugging with KVM >> cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code >> target/arm: Move cortex sysregs into cpregs.c >> tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI >> tests/avocado: Skip tests that require a missing accelerator >> tests/avocado: Tag TCG tests with accel:tcg > > Testing on Darwin: > > 14/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/test-hmp > > ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code > should not be reached > 17/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/qom-test > qemu-system-aarch64: unknown type 'arm-gicv3' > 18/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/boot-serial-test > qemu-system-aarch64: -accel tcg: invalid accelerator tcg > 19/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/vnc-display-test > qemu-system-aarch64: No machine specified, and there is no default > 20/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/migration-test > qemu-system-aarch64: -accel tcg: invalid accelerator tcg > > Reproducers: > > $ ./qemu-system-aarch64 -display none -S -M mps3-an547 -accel qtest > -monitor stdio > QEMU 7.2.50 monitor - type 'help' for more information > (qemu) gva2gpa 0 > ** > ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code > should not be reached > Bail out! > ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code > should not be reached > Abort trap: 6 > > frame #4: 0x0000000101fdd6cc > libglib-2.0.0.dylib`g_assertion_message_expr + 116 > frame #5: 0x0000000100360ce0 > qemu-system-aarch64`arm_v7m_mmu_idx_for_secstate(env=<unavailable>, > secstate=<unavailable>) at helper.c:2495:5 > frame #6: 0x000000010035f7f4 > qemu-system-aarch64`arm_mmu_idx_el(env=<unavailable>, el=<unavailable>) > at helper.c:2514:16 > frame #7: 0x00000001002d17ec > qemu-system-aarch64`arm_cpu_get_phys_page_attrs_debug(cs=<unavailable>, > addr=0, attrs=0x000000016fdfda50) at ptw.c:2982:23 > frame #8: 0x00000001003c660c > qemu-system-aarch64`hmp_gva2gpa(mon=0x000060000390f0c0, > qdict=<unavailable>) at misc.c:714:12 > > $ ./qemu-system-aarch64 -display none -machine sbsa-ref -accel qtest > qemu-system-aarch64: unknown type 'arm-gicv3' > Abort trap: 6 > > frame #2: 0x00000001958522c8 libsystem_c.dylib`abort + 180 > frame #3: 0x00000001003d32e8 > qemu-system-aarch64`qdev_new(name="arm-gicv3") at qdev.c:164:9 > frame #4: 0x00000001002f30d4 qemu-system-aarch64`sbsa_ref_init > [inlined] create_gic(sms=0x0000000103ff0d10) at sbsa-ref.c:405:16 > frame #5: 0x00000001002f30a0 > qemu-system-aarch64`sbsa_ref_init(machine=0x0000000103ff0d10) at > sbsa-ref.c:773:5 > frame #6: 0x00000001000905c0 > qemu-system-aarch64`machine_run_board_init(machine=0x0000000103ff0d10, > mem_path=<unavailable>, errp=<unavailable>) at machine.c:1404:5 Are these errors without TCG? If so they will be fixed by the other half of the series by removing the machines/cpus that depend on TCG. Nothing against fixing this now in the specific tests, of course, but a user on the cmdline would also hit these.
On 19/1/23 08:41, Philippe Mathieu-Daudé wrote: > On 18/1/23 20:34, Fabiano Rosas wrote: >> These are the already reviewed patches from the first half of my >> previous series: >> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >> >> This unbreaks the --disable-tcg build, but there are issues in runtime >> that are still being hashed out in the other series. >> >> For the build _with_ TCG, this should behave the same as master. > Reproducers: > > $ ./qemu-system-aarch64 -display none -S -M mps3-an547 -accel qtest > -monitor stdio > QEMU 7.2.50 monitor - type 'help' for more information > (qemu) gva2gpa 0 > ** > ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code > should not be reached > Bail out! > ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code > should not be reached > Abort trap: 6 > > frame #4: 0x0000000101fdd6cc > libglib-2.0.0.dylib`g_assertion_message_expr + 116 > frame #5: 0x0000000100360ce0 > qemu-system-aarch64`arm_v7m_mmu_idx_for_secstate(env=<unavailable>, > secstate=<unavailable>) at helper.c:2495:5 > frame #6: 0x000000010035f7f4 > qemu-system-aarch64`arm_mmu_idx_el(env=<unavailable>, el=<unavailable>) > at helper.c:2514:16 > frame #7: 0x00000001002d17ec > qemu-system-aarch64`arm_cpu_get_phys_page_attrs_debug(cs=<unavailable>, > addr=0, attrs=0x000000016fdfda50) at ptw.c:2982:23 > frame #8: 0x00000001003c660c > qemu-system-aarch64`hmp_gva2gpa(mon=0x000060000390f0c0, > qdict=<unavailable>) at misc.c:714:12 This problem was previously fixed by this series: https://www.mail-archive.com/qemu-devel@nongnu.org/msg777719.html In particular by this patch: https://www.mail-archive.com/qemu-devel@nongnu.org/msg777724.html Since all issues have been identified: Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On 19/1/23 13:32, Fabiano Rosas wrote: > Philippe Mathieu-Daudé <philmd@linaro.org> writes: > >> On 18/1/23 20:34, Fabiano Rosas wrote: >>> These are the already reviewed patches from the first half of my >>> previous series: >>> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >>> >>> This unbreaks the --disable-tcg build, but there are issues in runtime >>> that are still being hashed out in the other series. Are you saying, we can *link* this configuration but not *run* it yet? >>> For the build _with_ TCG, this should behave the same as master. >>> >>> Based on Richard's "target/arm: Introduce aarch64_set_svcr": >>> https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org >>> >>> Claudio Fontana (5): >>> target/arm: rename handle_semihosting to tcg_handle_semihosting >>> target/arm: wrap psci call with tcg_enabled >>> target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() >>> target/arm: move helpers to tcg/ >>> target/arm: Move psci.c into the tcg directory >>> >>> Fabiano Rosas (15): >>> target/arm: Move PC alignment check >>> target/arm: Move cpregs code out of cpu.h >>> target/arm: Move cpregs code into cpregs.c >>> target/arm: Move define_debug_regs() to cpregs.c >>> target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled >>> target/arm: move translate modules to tcg/ >>> target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled >>> target/arm: Move hflags code into the tcg directory >>> target/arm: Move regime_using_lpae_format into internal.h >>> target/arm: Don't access TCG code when debugging with KVM >>> cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code >>> target/arm: Move cortex sysregs into cpregs.c >>> tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI >>> tests/avocado: Skip tests that require a missing accelerator >>> tests/avocado: Tag TCG tests with accel:tcg >> >> Testing on Darwin: >> >> 14/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/test-hmp >> >> ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code >> should not be reached >> 17/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/qom-test >> qemu-system-aarch64: unknown type 'arm-gicv3' >> 18/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/boot-serial-test >> qemu-system-aarch64: -accel tcg: invalid accelerator tcg >> 19/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/vnc-display-test >> qemu-system-aarch64: No machine specified, and there is no default >> 20/20 qemu:qtest+qtest-aarch64 / qtest-aarch64/migration-test >> qemu-system-aarch64: -accel tcg: invalid accelerator tcg >> >> Reproducers: >> >> $ ./qemu-system-aarch64 -display none -S -M mps3-an547 -accel qtest >> -monitor stdio >> QEMU 7.2.50 monitor - type 'help' for more information >> (qemu) gva2gpa 0 >> ** >> ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code >> should not be reached >> Bail out! >> ERROR:../../target/arm/helper.c:2495:arm_v7m_mmu_idx_for_secstate: code >> should not be reached >> Abort trap: 6 >> >> frame #4: 0x0000000101fdd6cc >> libglib-2.0.0.dylib`g_assertion_message_expr + 116 >> frame #5: 0x0000000100360ce0 >> qemu-system-aarch64`arm_v7m_mmu_idx_for_secstate(env=<unavailable>, >> secstate=<unavailable>) at helper.c:2495:5 >> frame #6: 0x000000010035f7f4 >> qemu-system-aarch64`arm_mmu_idx_el(env=<unavailable>, el=<unavailable>) >> at helper.c:2514:16 >> frame #7: 0x00000001002d17ec >> qemu-system-aarch64`arm_cpu_get_phys_page_attrs_debug(cs=<unavailable>, >> addr=0, attrs=0x000000016fdfda50) at ptw.c:2982:23 >> frame #8: 0x00000001003c660c >> qemu-system-aarch64`hmp_gva2gpa(mon=0x000060000390f0c0, >> qdict=<unavailable>) at misc.c:714:12 >> >> $ ./qemu-system-aarch64 -display none -machine sbsa-ref -accel qtest >> qemu-system-aarch64: unknown type 'arm-gicv3' >> Abort trap: 6 >> >> frame #2: 0x00000001958522c8 libsystem_c.dylib`abort + 180 >> frame #3: 0x00000001003d32e8 >> qemu-system-aarch64`qdev_new(name="arm-gicv3") at qdev.c:164:9 >> frame #4: 0x00000001002f30d4 qemu-system-aarch64`sbsa_ref_init >> [inlined] create_gic(sms=0x0000000103ff0d10) at sbsa-ref.c:405:16 >> frame #5: 0x00000001002f30a0 >> qemu-system-aarch64`sbsa_ref_init(machine=0x0000000103ff0d10) at >> sbsa-ref.c:773:5 >> frame #6: 0x00000001000905c0 >> qemu-system-aarch64`machine_run_board_init(machine=0x0000000103ff0d10, >> mem_path=<unavailable>, errp=<unavailable>) at machine.c:1404:5 > > Are these errors without TCG? Yes. > If so they will be fixed by the other half > of the series by removing the machines/cpus that depend on TCG. Nothing > against fixing this now in the specific tests, of course, but a user on > the cmdline would also hit these. I ran 'make check' which calls 'make check-qtest' -> 'make check-qtest-aarch64'.
Philippe Mathieu-Daudé <philmd@linaro.org> writes: > On 19/1/23 13:32, Fabiano Rosas wrote: >> Philippe Mathieu-Daudé <philmd@linaro.org> writes: >> >>> On 18/1/23 20:34, Fabiano Rosas wrote: >>>> These are the already reviewed patches from the first half of my >>>> previous series: >>>> https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de >>>> >>>> This unbreaks the --disable-tcg build, but there are issues in runtime >>>> that are still being hashed out in the other series. > > Are you saying, we can *link* this configuration but not *run* it yet? Strictly speaking, we cannot run it. While it works most of the time, there are still references to machines and cpus that are TCG-only. Try running -machine ? or -cpu ? for instance. If a user tries to pass one of those, there might be breakages like the ones you saw. The other series (I just sent a v4) removes everything that depends on TCG. Then it will be 100% safe to use --disable-tcg and consume the result.
On 18/1/23 20:34, Fabiano Rosas wrote: > These are the already reviewed patches from the first half of my > previous series: > https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de > > This unbreaks the --disable-tcg build, but there are issues in runtime > that are still being hashed out in the other series. > > For the build _with_ TCG, this should behave the same as master. If you respin, please include this build-only CI test to avoid your work to bitrot until the rest is merged: https://lore.kernel.org/qemu-devel/20230119155646.50503-1-philmd@linaro.org/ Peter, if this is good enough for you please consider the CI patch on top of this series. Regards, Phil.
These are the already reviewed patches from the first half of my previous series: https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de This unbreaks the --disable-tcg build, but there are issues in runtime that are still being hashed out in the other series. For the build _with_ TCG, this should behave the same as master. Based on Richard's "target/arm: Introduce aarch64_set_svcr": https://lore.kernel.org/r/20230112004322.161330-1-richard.henderson@linaro.org Claudio Fontana (5): target/arm: rename handle_semihosting to tcg_handle_semihosting target/arm: wrap psci call with tcg_enabled target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() target/arm: move helpers to tcg/ target/arm: Move psci.c into the tcg directory Fabiano Rosas (15): target/arm: Move PC alignment check target/arm: Move cpregs code out of cpu.h target/arm: Move cpregs code into cpregs.c target/arm: Move define_debug_regs() to cpregs.c target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled target/arm: move translate modules to tcg/ target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled target/arm: Move hflags code into the tcg directory target/arm: Move regime_using_lpae_format into internal.h target/arm: Don't access TCG code when debugging with KVM cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code target/arm: Move cortex sysregs into cpregs.c tests/qtest: Restrict bcm2835-dma-test to CONFIG_RASPI tests/avocado: Skip tests that require a missing accelerator tests/avocado: Tag TCG tests with accel:tcg MAINTAINERS | 1 + hw/arm/boot.c | 6 +- hw/intc/armv7m_nvic.c | 20 +- include/exec/cpu-defs.h | 6 + target/arm/arm-powerctl.c | 7 +- target/arm/cpregs.c | 9533 +++++++++++++++++++++++ target/arm/cpregs.h | 104 + target/arm/cpu.c | 9 +- target/arm/cpu.h | 91 - target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 59 - target/arm/helper.c | 9461 +--------------------- target/arm/internals.h | 38 +- target/arm/machine.c | 30 +- target/arm/meson.build | 48 +- target/arm/ptw.c | 4 + target/arm/tcg-stubs.c | 27 + target/arm/{ => tcg}/a32-uncond.decode | 0 target/arm/{ => tcg}/a32.decode | 0 target/arm/{ => tcg}/crypto_helper.c | 0 target/arm/{ => tcg}/debug_helper.c | 367 - target/arm/{ => tcg}/helper-a64.c | 0 target/arm/tcg/hflags.c | 370 + target/arm/{ => tcg}/iwmmxt_helper.c | 0 target/arm/{ => tcg}/m-nocp.decode | 0 target/arm/{ => tcg}/m_helper.c | 0 target/arm/tcg/meson.build | 51 + target/arm/{ => tcg}/mte_helper.c | 0 target/arm/{ => tcg}/mve.decode | 0 target/arm/{ => tcg}/mve_helper.c | 0 target/arm/{ => tcg}/neon-dp.decode | 0 target/arm/{ => tcg}/neon-ls.decode | 0 target/arm/{ => tcg}/neon-shared.decode | 0 target/arm/{ => tcg}/neon_helper.c | 0 target/arm/{ => tcg}/op_helper.c | 0 target/arm/{ => tcg}/pauth_helper.c | 0 target/arm/{ => tcg}/psci.c | 0 target/arm/{ => tcg}/sme-fa64.decode | 0 target/arm/{ => tcg}/sme.decode | 0 target/arm/{ => tcg}/sme_helper.c | 0 target/arm/{ => tcg}/sve.decode | 0 target/arm/{ => tcg}/sve_helper.c | 0 target/arm/{ => tcg}/t16.decode | 0 target/arm/{ => tcg}/t32.decode | 0 target/arm/{ => tcg}/tlb_helper.c | 18 - target/arm/{ => tcg}/translate-a64.c | 0 target/arm/{ => tcg}/translate-a64.h | 0 target/arm/{ => tcg}/translate-m-nocp.c | 0 target/arm/{ => tcg}/translate-mve.c | 0 target/arm/{ => tcg}/translate-neon.c | 0 target/arm/{ => tcg}/translate-sme.c | 0 target/arm/{ => tcg}/translate-sve.c | 0 target/arm/{ => tcg}/translate-vfp.c | 0 target/arm/{ => tcg}/translate.c | 0 target/arm/{ => tcg}/translate.h | 0 target/arm/{ => tcg}/vec_helper.c | 0 target/arm/{ => tcg}/vec_internal.h | 0 target/arm/{ => tcg}/vfp-uncond.decode | 0 target/arm/{ => tcg}/vfp.decode | 0 target/arm/trace-events | 2 +- tests/avocado/avocado_qemu/__init__.py | 4 + tests/avocado/boot_linux_console.py | 1 + tests/avocado/reverse_debugging.py | 8 + tests/qtest/meson.build | 4 +- 64 files changed, 10210 insertions(+), 10060 deletions(-) create mode 100644 target/arm/cpregs.c create mode 100644 target/arm/tcg-stubs.c rename target/arm/{ => tcg}/a32-uncond.decode (100%) rename target/arm/{ => tcg}/a32.decode (100%) rename target/arm/{ => tcg}/crypto_helper.c (100%) rename target/arm/{ => tcg}/debug_helper.c (63%) rename target/arm/{ => tcg}/helper-a64.c (100%) create mode 100644 target/arm/tcg/hflags.c rename target/arm/{ => tcg}/iwmmxt_helper.c (100%) rename target/arm/{ => tcg}/m-nocp.decode (100%) rename target/arm/{ => tcg}/m_helper.c (100%) create mode 100644 target/arm/tcg/meson.build rename target/arm/{ => tcg}/mte_helper.c (100%) rename target/arm/{ => tcg}/mve.decode (100%) rename target/arm/{ => tcg}/mve_helper.c (100%) rename target/arm/{ => tcg}/neon-dp.decode (100%) rename target/arm/{ => tcg}/neon-ls.decode (100%) rename target/arm/{ => tcg}/neon-shared.decode (100%) rename target/arm/{ => tcg}/neon_helper.c (100%) rename target/arm/{ => tcg}/op_helper.c (100%) rename target/arm/{ => tcg}/pauth_helper.c (100%) rename target/arm/{ => tcg}/psci.c (100%) rename target/arm/{ => tcg}/sme-fa64.decode (100%) rename target/arm/{ => tcg}/sme.decode (100%) rename target/arm/{ => tcg}/sme_helper.c (100%) rename target/arm/{ => tcg}/sve.decode (100%) rename target/arm/{ => tcg}/sve_helper.c (100%) rename target/arm/{ => tcg}/t16.decode (100%) rename target/arm/{ => tcg}/t32.decode (100%) rename target/arm/{ => tcg}/tlb_helper.c (94%) rename target/arm/{ => tcg}/translate-a64.c (100%) rename target/arm/{ => tcg}/translate-a64.h (100%) rename target/arm/{ => tcg}/translate-m-nocp.c (100%) rename target/arm/{ => tcg}/translate-mve.c (100%) rename target/arm/{ => tcg}/translate-neon.c (100%) rename target/arm/{ => tcg}/translate-sme.c (100%) rename target/arm/{ => tcg}/translate-sve.c (100%) rename target/arm/{ => tcg}/translate-vfp.c (100%) rename target/arm/{ => tcg}/translate.c (100%) rename target/arm/{ => tcg}/translate.h (100%) rename target/arm/{ => tcg}/vec_helper.c (100%) rename target/arm/{ => tcg}/vec_internal.h (100%) rename target/arm/{ => tcg}/vfp-uncond.decode (100%) rename target/arm/{ => tcg}/vfp.decode (100%)