diff mbox series

[3/6] drm: rcar-du: Fix LVDS stop sequence

Message ID 20230117135154.387208-4-tomi.valkeinen+renesas@ideasonboard.com (mailing list archive)
State New, archived
Headers show
Series drm: rcar-du: Misc patches | expand

Commit Message

Tomi Valkeinen Jan. 17, 2023, 1:51 p.m. UTC 
From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>

According to H/W manual, LVDCR0 register must be cleared bit by bit when
disabling LVDS.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
[tomi.valkeinen: simplified the code a bit]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
 drivers/gpu/drm/rcar-du/rcar_lvds.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

Comments

Laurent Pinchart Jan. 18, 2023, 9:12 p.m. UTC | #1 
Hi Tomi,

Thank you for the patch.

On Tue, Jan 17, 2023 at 03:51:51PM +0200, Tomi Valkeinen wrote:
> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> 
> According to H/W manual, LVDCR0 register must be cleared bit by bit when

s@H/W@the hardware/

> disabling LVDS.

I don't like this much, but I think I'll stop fighting :-)

> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
> [tomi.valkeinen: simplified the code a bit]
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> ---
>  drivers/gpu/drm/rcar-du/rcar_lvds.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
> index 674b727cdaa2..01800cef1c33 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
> @@ -87,6 +87,11 @@ static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
>  	iowrite32(data, lvds->mmio + reg);
>  }
>  
> +static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
> +{
> +	return ioread32(lvds->mmio + reg);
> +}

Could you please move read before write ?

> +
>  /* -----------------------------------------------------------------------------
>   * PLL Setup
>   */
> @@ -549,8 +554,28 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
>  				     struct drm_bridge_state *old_bridge_state)
>  {
>  	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
> +	u32 lvdcr0;
> +
> +	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
> +
> +	lvdcr0 &= ~LVDCR0_LVRES;
> +	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> +
> +	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
> +		lvdcr0 &= ~LVDCR0_LVEN;
> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> +	}
> +
> +	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
> +		lvdcr0 &= ~LVDCR0_PWD;
> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> +	}
> +
> +	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
> +		lvdcr0 &= ~LVDCR0_PLLON;
> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> +	}

This will leave LVDCR0_BEN and LVDCR0_LVEN on Gen2. Is that fine ?

>  
> -	rcar_lvds_write(lvds, LVDCR0, 0);
>  	rcar_lvds_write(lvds, LVDCR1, 0);
>  	rcar_lvds_write(lvds, LVDPLLCR, 0);
>
Tomi Valkeinen Jan. 19, 2023, 8:49 a.m. UTC | #2 
On 18/01/2023 23:12, Laurent Pinchart wrote:
> Hi Tomi,
> 
> Thank you for the patch.
> 
> On Tue, Jan 17, 2023 at 03:51:51PM +0200, Tomi Valkeinen wrote:
>> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
>>
>> According to H/W manual, LVDCR0 register must be cleared bit by bit when
> 
> s@H/W@the hardware/
> 
>> disabling LVDS.
> 
> I don't like this much, but I think I'll stop fighting :-)
> 
>> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
>> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
>> [tomi.valkeinen: simplified the code a bit]
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
>> ---
>>   drivers/gpu/drm/rcar-du/rcar_lvds.c | 27 ++++++++++++++++++++++++++-
>>   1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
>> index 674b727cdaa2..01800cef1c33 100644
>> --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
>> +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
>> @@ -87,6 +87,11 @@ static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
>>   	iowrite32(data, lvds->mmio + reg);
>>   }
>>   
>> +static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
>> +{
>> +	return ioread32(lvds->mmio + reg);
>> +}
> 
> Could you please move read before write ?

Sure.

>> +
>>   /* -----------------------------------------------------------------------------
>>    * PLL Setup
>>    */
>> @@ -549,8 +554,28 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
>>   				     struct drm_bridge_state *old_bridge_state)
>>   {
>>   	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
>> +	u32 lvdcr0;
>> +
>> +	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
>> +
>> +	lvdcr0 &= ~LVDCR0_LVRES;
>> +	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
>> +
>> +	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
>> +		lvdcr0 &= ~LVDCR0_LVEN;
>> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
>> +	}
>> +
>> +	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
>> +		lvdcr0 &= ~LVDCR0_PWD;
>> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
>> +	}
>> +
>> +	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
>> +		lvdcr0 &= ~LVDCR0_PLLON;
>> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
>> +	}
> 
> This will leave LVDCR0_BEN and LVDCR0_LVEN on Gen2. Is that fine ?

I don't know, I don't have the manuals or HW. But your point is a bit 
worrying.

I think we can just do a rcar_lvds_write(lvds, LVDCR0, 0) after the 
above shenanigans, to make sure everything is disabled. The HW manual 
doesn't tell us to do that, though, on gen3. Do you think that will be a 
problem?

And I'm not fully serious with the last sentence...

  Tomi
Laurent Pinchart Jan. 19, 2023, 10:48 a.m. UTC | #3 
Hi Tomi,

On Thu, Jan 19, 2023 at 10:49:28AM +0200, Tomi Valkeinen wrote:
> On 18/01/2023 23:12, Laurent Pinchart wrote:
> > On Tue, Jan 17, 2023 at 03:51:51PM +0200, Tomi Valkeinen wrote:
> >> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> >>
> >> According to H/W manual, LVDCR0 register must be cleared bit by bit when
> > 
> > s@H/W@the hardware/
> > 
> >> disabling LVDS.
> > 
> > I don't like this much, but I think I'll stop fighting :-)
> > 
> >> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> >> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
> >> [tomi.valkeinen: simplified the code a bit]
> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> >> ---
> >>   drivers/gpu/drm/rcar-du/rcar_lvds.c | 27 ++++++++++++++++++++++++++-
> >>   1 file changed, 26 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
> >> index 674b727cdaa2..01800cef1c33 100644
> >> --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
> >> +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
> >> @@ -87,6 +87,11 @@ static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
> >>   	iowrite32(data, lvds->mmio + reg);
> >>   }
> >>   
> >> +static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
> >> +{
> >> +	return ioread32(lvds->mmio + reg);
> >> +}
> > 
> > Could you please move read before write ?
> 
> Sure.
> 
> >> +
> >>   /* -----------------------------------------------------------------------------
> >>    * PLL Setup
> >>    */
> >> @@ -549,8 +554,28 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
> >>   				     struct drm_bridge_state *old_bridge_state)
> >>   {
> >>   	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
> >> +	u32 lvdcr0;
> >> +
> >> +	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
> >> +
> >> +	lvdcr0 &= ~LVDCR0_LVRES;
> >> +	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> >> +
> >> +	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
> >> +		lvdcr0 &= ~LVDCR0_LVEN;
> >> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> >> +	}
> >> +
> >> +	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
> >> +		lvdcr0 &= ~LVDCR0_PWD;
> >> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> >> +	}
> >> +
> >> +	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
> >> +		lvdcr0 &= ~LVDCR0_PLLON;
> >> +		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
> >> +	}
> > 
> > This will leave LVDCR0_BEN and LVDCR0_LVEN on Gen2. Is that fine ?
> 
> I don't know, I don't have the manuals or HW. But your point is a bit 
> worrying.
> 
> I think we can just do a rcar_lvds_write(lvds, LVDCR0, 0) after the 
> above shenanigans, to make sure everything is disabled. The HW manual 
> doesn't tell us to do that, though, on gen3. Do you think that will be a 
> problem?
> 
> And I'm not fully serious with the last sentence...

:-)

A write(lvds, LVDCR0, 0) should fix it, I'm fine with that.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index 674b727cdaa2..01800cef1c33 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -87,6 +87,11 @@  static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
 	iowrite32(data, lvds->mmio + reg);
 }
 
+static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
+{
+	return ioread32(lvds->mmio + reg);
+}
+
 /* -----------------------------------------------------------------------------
  * PLL Setup
  */
@@ -549,8 +554,28 @@  static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
 				     struct drm_bridge_state *old_bridge_state)
 {
 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
+	u32 lvdcr0;
+
+	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
+
+	lvdcr0 &= ~LVDCR0_LVRES;
+	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+
+	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
+		lvdcr0 &= ~LVDCR0_LVEN;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
+
+	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
+		lvdcr0 &= ~LVDCR0_PWD;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
+
+	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
+		lvdcr0 &= ~LVDCR0_PLLON;
+		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+	}
 
-	rcar_lvds_write(lvds, LVDCR0, 0);
 	rcar_lvds_write(lvds, LVDCR1, 0);
 	rcar_lvds_write(lvds, LVDPLLCR, 0);