| Message ID | 20230120193457.3295977-5-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add _PICK_EVEN_2RANGES | expand |
Verified that the new macro evaluates to the right register offsets. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas > De Marchi > Sent: Friday, January 20, 2023 11:35 AM > To: intel-gfx@lists.freedesktop.org > Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri- > devel@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with > _PICK_EVEN_2RANGES() > > As done previously for pll, also convert users of _PHY3() to > _PICK_EVEN_2RANGES(). Size comparison of i915.o: > > $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} > text data bss dec hex filename > 4026997 185703 6984 4219684 406324 > build64/drivers/gpu/drm/i915/i915.o.old > 4026288 185703 6984 4218975 40605f > build64/drivers/gpu/drm/i915/i915.o.new > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > .../drm/i915/display/intel_display_reg_defs.h | 3 --- > drivers/gpu/drm/i915/i915_reg.h | 16 +++++++++------- > 2 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > index a4ed1c530799..f1681e1396b5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > @@ -29,11 +29,8 @@ > #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) > #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) > > -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) > - > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > -#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > /* > * Device info offset array based helpers for groups of registers with unevenly > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index dd1eb8b10e0e..fe6385443c4a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -541,9 +541,10 @@ > #define _BXT_PHY0_BASE 0x6C000 > #define _BXT_PHY1_BASE 0x162000 > #define _BXT_PHY2_BASE 0x163000 > -#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ > - _BXT_PHY1_BASE, \ > - _BXT_PHY2_BASE) > +#define BXT_PHY_BASE(phy) > \ > + _PICK_EVEN_2RANGES(phy, 1, > \ > + _BXT_PHY0_BASE, _BXT_PHY0_BASE, > \ > + _BXT_PHY1_BASE, _BXT_PHY2_BASE) > > #define _BXT_PHY(phy, reg) \ > _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) @@ -566,13 > +567,14 @@ > #define BXT_PHY_CTL(port) _MMIO_PORT(port, > _BXT_PHY_CTL_DDI_A, \ > > _BXT_PHY_CTL_DDI_B) > > -#define _PHY_CTL_FAMILY_EDP 0x64C80 > #define _PHY_CTL_FAMILY_DDI 0x64C90 > +#define _PHY_CTL_FAMILY_EDP 0x64C80 > #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 > #define COMMON_RESET_DIS (1 << 31) > -#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), > _PHY_CTL_FAMILY_DDI, \ > - > _PHY_CTL_FAMILY_EDP, \ > - > _PHY_CTL_FAMILY_DDI_C) > +#define BXT_PHY_CTL_FAMILY(phy) > \ > + _MMIO(_PICK_EVEN_2RANGES(phy, 1, > \ > + _PHY_CTL_FAMILY_DDI, > _PHY_CTL_FAMILY_DDI, \ > + _PHY_CTL_FAMILY_EDP, > _PHY_CTL_FAMILY_DDI_C)) > > /* BXT PHY PLL registers */ > #define _PORT_PLL_A 0x46074 > -- > 2.39.0
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index a4ed1c530799..f1681e1396b5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -29,11 +29,8 @@ #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) - #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) -#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dd1eb8b10e0e..fe6385443c4a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -541,9 +541,10 @@ #define _BXT_PHY0_BASE 0x6C000 #define _BXT_PHY1_BASE 0x162000 #define _BXT_PHY2_BASE 0x163000 -#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ - _BXT_PHY1_BASE, \ - _BXT_PHY2_BASE) +#define BXT_PHY_BASE(phy) \ + _PICK_EVEN_2RANGES(phy, 1, \ + _BXT_PHY0_BASE, _BXT_PHY0_BASE, \ + _BXT_PHY1_BASE, _BXT_PHY2_BASE) #define _BXT_PHY(phy, reg) \ _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) @@ -566,13 +567,14 @@ #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ _BXT_PHY_CTL_DDI_B) -#define _PHY_CTL_FAMILY_EDP 0x64C80 #define _PHY_CTL_FAMILY_DDI 0x64C90 +#define _PHY_CTL_FAMILY_EDP 0x64C80 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 #define COMMON_RESET_DIS (1 << 31) -#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ - _PHY_CTL_FAMILY_EDP, \ - _PHY_CTL_FAMILY_DDI_C) +#define BXT_PHY_CTL_FAMILY(phy) \ + _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ + _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ + _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) /* BXT PHY PLL registers */ #define _PORT_PLL_A 0x46074
As done previously for pll, also convert users of _PHY3() to _PICK_EVEN_2RANGES(). Size comparison of i915.o: $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} text data bss dec hex filename 4026997 185703 6984 4219684 406324 build64/drivers/gpu/drm/i915/i915.o.old 4026288 185703 6984 4218975 40605f build64/drivers/gpu/drm/i915/i915.o.new Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- .../drm/i915/display/intel_display_reg_defs.h | 3 --- drivers/gpu/drm/i915/i915_reg.h | 16 +++++++++------- 2 files changed, 9 insertions(+), 10 deletions(-)