| Message ID | 20230120210101.2146852-6-konrad.dybcio@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/8] drm/msm/dsi: Allow 2 CTRLs on v2.5.0 | expand |
On 20/01/2023 23:00, Konrad Dybcio wrote: > As downstream indicates, DSI PLL is actually 0x27c and not 0x260- > wide. Fix that to reserve the correct registers. > > Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 22bf6239c757..b09eb8880376 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3041,7 +3041,7 @@ mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,sm8350-dsi-phy-5nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, - <0 0x0ae94900 0 0x260>; + <0 0x0ae94900 0 0x27c>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -3138,7 +3138,7 @@ mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,sm8350-dsi-phy-5nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x260>; + <0 0x0ae96900 0 0x27c>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll";
As downstream indicates, DSI PLL is actually 0x27c and not 0x260- wide. Fix that to reserve the correct registers. Fixes: d4a4410583ed ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)