| Message ID | 20230120151551.1022761-1-philipp.tomsich@vrull.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] target/riscv: update disas.c for xnor/orn/andn and slli.uw | expand |
On Sat, Jan 21, 2023 at 1:16 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > The decoding of the following instructions from Zb[abcs] currently > contains decoding/printing errors: > * xnor,orn,andn: the rs2 operand is not being printed > * slli.uw: decodes and prints the immediate shift-amount as a > register (e.g. 'shift-by-2' becomes 'sp') instead of > interpreting this as an immediate > > This commit updates the instruction descriptions to use the > appropriate decoding/printing formats. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > disas/riscv.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index d216b9c39b..ddda687c13 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1626,9 +1626,9 @@ const rv_opcode_data opcode_data[] = { > { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > + { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > -- > 2.34.1 > >
On Sat, Jan 21, 2023 at 1:16 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > The decoding of the following instructions from Zb[abcs] currently > contains decoding/printing errors: > * xnor,orn,andn: the rs2 operand is not being printed > * slli.uw: decodes and prints the immediate shift-amount as a > register (e.g. 'shift-by-2' becomes 'sp') instead of > interpreting this as an immediate > > This commit updates the instruction descriptions to use the > appropriate decoding/printing formats. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Thanks! Applied to riscv-to-apply.next Alistair > > --- > > disas/riscv.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index d216b9c39b..ddda687c13 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1626,9 +1626,9 @@ const rv_opcode_data opcode_data[] = { > { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > + { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > + { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > -- > 2.34.1 > >
diff --git a/disas/riscv.c b/disas/riscv.c index d216b9c39b..ddda687c13 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1626,9 +1626,9 @@ const rv_opcode_data opcode_data[] = { { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
The decoding of the following instructions from Zb[abcs] currently contains decoding/printing errors: * xnor,orn,andn: the rs2 operand is not being printed * slli.uw: decodes and prints the immediate shift-amount as a register (e.g. 'shift-by-2' becomes 'sp') instead of interpreting this as an immediate This commit updates the instruction descriptions to use the appropriate decoding/printing formats. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- disas/riscv.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)