| Message ID | 20230120193457.3295977-4-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add _PICK_EVEN_2RANGES | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas > De Marchi > Sent: Friday, January 20, 2023 11:35 AM > To: intel-gfx@lists.freedesktop.org > Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri- > devel@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to > _PICK_EVEN_2RANGES > > Avoid the array lookup, converting the PLL macros after ICL to > _PICK_EVEN_RANGES. This provides the following reduction in code size: > > $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} > text data bss dec hex filename > 4027456 185703 6984 4220143 4064ef > build64/drivers/gpu/drm/i915/i915.o.old > 4026997 185703 6984 4219684 406324 > build64/drivers/gpu/drm/i915/i915.o.new > > At the same time it's safer, avoiding out-of-bounds array access. This allows to > remove _MMIO_PLL3() that is now unused. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > .../drm/i915/display/intel_display_reg_defs.h | 1 - > drivers/gpu/drm/i915/i915_reg.h | 59 +++++++++---------- > 2 files changed, 29 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > index 02605418ff08..a4ed1c530799 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h > @@ -34,7 +34,6 @@ > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > -#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) > > /* > * Device info offset array based helpers for groups of registers with unevenly > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8da3546d82fb..dd1eb8b10e0e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7232,13 +7232,15 @@ enum skl_power_gate { > #define PLL_LOCK REG_BIT(30) > #define PLL_POWER_ENABLE REG_BIT(27) > #define PLL_POWER_STATE REG_BIT(26) > -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, > _DPLL1_ENABLE, \ > - _ADLS_DPLL2_ENABLE, > _ADLS_DPLL3_ENABLE) > +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, > \ > + _DPLL0_ENABLE, > _DPLL1_ENABLE, \ > + > _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) > > #define _DG2_PLL3_ENABLE 0x4601C > > -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, > _DPLL1_ENABLE, \ > - _ADLS_DPLL2_ENABLE, > _DG2_PLL3_ENABLE) > +#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, > \ > + _DPLL0_ENABLE, > _DPLL1_ENABLE, \ > + _DG2_PLL3_ENABLE, > _DG2_PLL3_ENABLE)) > > #define TBT_PLL_ENABLE _MMIO(0x46020) > > @@ -7251,8 +7253,9 @@ enum skl_power_gate { > _MG_PLL2_ENABLE) > > /* DG1 PLL */ > -#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, > _DPLL1_ENABLE, \ > - _MG_PLL1_ENABLE, > _MG_PLL2_ENABLE) > +#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, > \ > + _DPLL0_ENABLE, > _DPLL1_ENABLE, \ > + _MG_PLL1_ENABLE, > _MG_PLL2_ENABLE)) > > /* ADL-P Type C PLL */ > #define PORTTC1_PLL_ENABLE 0x46038 > @@ -7312,9 +7315,9 @@ enum skl_power_gate { > #define _TGL_DPLL0_CFGCR0 0x164284 > #define _TGL_DPLL1_CFGCR0 0x16428C > #define _TGL_TBTPLL_CFGCR0 0x16429C > -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, > _TGL_DPLL0_CFGCR0, \ > - _TGL_DPLL1_CFGCR0, \ > - _TGL_TBTPLL_CFGCR0) > +#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, > \ > + _TGL_DPLL0_CFGCR0, > _TGL_DPLL1_CFGCR0, \ > + _TGL_TBTPLL_CFGCR0, > _TGL_TBTPLL_CFGCR0)) > #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, > \ > _TGL_DPLL1_CFGCR0) > > @@ -7327,40 +7330,36 @@ enum skl_power_gate { > #define _TGL_DPLL0_CFGCR1 0x164288 > #define _TGL_DPLL1_CFGCR1 0x164290 > #define _TGL_TBTPLL_CFGCR1 0x1642A0 > -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, > _TGL_DPLL0_CFGCR1, \ > - _TGL_DPLL1_CFGCR1, \ > - _TGL_TBTPLL_CFGCR1) > +#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, > \ > + _TGL_DPLL0_CFGCR1, > _TGL_DPLL1_CFGCR1, \ > + _TGL_TBTPLL_CFGCR1, > _TGL_TBTPLL_CFGCR1)) > #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, > \ > _TGL_DPLL1_CFGCR1) > > #define _DG1_DPLL2_CFGCR0 0x16C284 > #define _DG1_DPLL3_CFGCR0 0x16C28C > -#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, > _TGL_DPLL0_CFGCR0, \ > - _TGL_DPLL1_CFGCR0, \ > - _DG1_DPLL2_CFGCR0, \ > - _DG1_DPLL3_CFGCR0) > +#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, > \ > + _TGL_DPLL0_CFGCR0, > _TGL_DPLL1_CFGCR0, \ > + _DG1_DPLL2_CFGCR0, > _DG1_DPLL3_CFGCR0)) > > #define _DG1_DPLL2_CFGCR1 0x16C288 > #define _DG1_DPLL3_CFGCR1 0x16C290 > -#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ > - _TGL_DPLL1_CFGCR1, \ > - _DG1_DPLL2_CFGCR1, \ > - _DG1_DPLL3_CFGCR1) > +#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, > \ > + _TGL_DPLL0_CFGCR1, > _TGL_DPLL1_CFGCR1, \ > + _DG1_DPLL2_CFGCR1, > _DG1_DPLL3_CFGCR1)) > > /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ > -#define _ADLS_DPLL3_CFGCR0 0x1642C0 > #define _ADLS_DPLL4_CFGCR0 0x164294 > -#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, > _TGL_DPLL0_CFGCR0, \ > - _TGL_DPLL1_CFGCR0, \ > - _ADLS_DPLL4_CFGCR0, \ > - _ADLS_DPLL3_CFGCR0) > +#define _ADLS_DPLL3_CFGCR0 0x1642C0 > +#define ADLS_DPLL_CFGCR0(pll) > _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ > + _TGL_DPLL0_CFGCR0, > _TGL_DPLL1_CFGCR0, \ > + _ADLS_DPLL4_CFGCR0, > _ADLS_DPLL3_CFGCR0)) > > -#define _ADLS_DPLL3_CFGCR1 0x1642C4 > #define _ADLS_DPLL4_CFGCR1 0x164298 > -#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, > _TGL_DPLL0_CFGCR1, \ > - _TGL_DPLL1_CFGCR1, \ > - _ADLS_DPLL4_CFGCR1, \ > - _ADLS_DPLL3_CFGCR1) > +#define _ADLS_DPLL3_CFGCR1 0x1642C4 > +#define ADLS_DPLL_CFGCR1(pll) > _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ > + _TGL_DPLL0_CFGCR1, > _TGL_DPLL1_CFGCR1, \ > + _ADLS_DPLL4_CFGCR1, > _ADLS_DPLL3_CFGCR1)) > > /* BXT display engine PLL */ > #define BXT_DE_PLL_CTL _MMIO(0x6d000) > -- > 2.39.0
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index 02605418ff08..a4ed1c530799 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -34,7 +34,6 @@ #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) -#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) /* * Device info offset array based helpers for groups of registers with unevenly diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8da3546d82fb..dd1eb8b10e0e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7232,13 +7232,15 @@ enum skl_power_gate { #define PLL_LOCK REG_BIT(30) #define PLL_POWER_ENABLE REG_BIT(27) #define PLL_POWER_STATE REG_BIT(26) -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) #define _DG2_PLL3_ENABLE 0x4601C -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) +#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -7251,8 +7253,9 @@ enum skl_power_gate { _MG_PLL2_ENABLE) /* DG1 PLL */ -#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) +#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) /* ADL-P Type C PLL */ #define PORTTC1_PLL_ENABLE 0x46038 @@ -7312,9 +7315,9 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR0 0x164284 #define _TGL_DPLL1_CFGCR0 0x16428C #define _TGL_TBTPLL_CFGCR0 0x16429C -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _TGL_TBTPLL_CFGCR0) +#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ _TGL_DPLL1_CFGCR0) @@ -7327,40 +7330,36 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR1 0x164288 #define _TGL_DPLL1_CFGCR1 0x164290 #define _TGL_TBTPLL_CFGCR1 0x1642A0 -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _TGL_TBTPLL_CFGCR1) +#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ _TGL_DPLL1_CFGCR1) #define _DG1_DPLL2_CFGCR0 0x16C284 #define _DG1_DPLL3_CFGCR0 0x16C28C -#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _DG1_DPLL2_CFGCR0, \ - _DG1_DPLL3_CFGCR0) +#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) #define _DG1_DPLL2_CFGCR1 0x16C288 #define _DG1_DPLL3_CFGCR1 0x16C290 -#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _DG1_DPLL2_CFGCR1, \ - _DG1_DPLL3_CFGCR1) +#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ -#define _ADLS_DPLL3_CFGCR0 0x1642C0 #define _ADLS_DPLL4_CFGCR0 0x164294 -#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _ADLS_DPLL4_CFGCR0, \ - _ADLS_DPLL3_CFGCR0) +#define _ADLS_DPLL3_CFGCR0 0x1642C0 +#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) -#define _ADLS_DPLL3_CFGCR1 0x1642C4 #define _ADLS_DPLL4_CFGCR1 0x164298 -#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _ADLS_DPLL4_CFGCR1, \ - _ADLS_DPLL3_CFGCR1) +#define _ADLS_DPLL3_CFGCR1 0x1642C4 +#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) /* BXT display engine PLL */ #define BXT_DE_PLL_CTL _MMIO(0x6d000)
Avoid the array lookup, converting the PLL macros after ICL to _PICK_EVEN_RANGES. This provides the following reduction in code size: $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} text data bss dec hex filename 4027456 185703 6984 4220143 4064ef build64/drivers/gpu/drm/i915/i915.o.old 4026997 185703 6984 4219684 406324 build64/drivers/gpu/drm/i915/i915.o.new At the same time it's safer, avoiding out-of-bounds array access. This allows to remove _MMIO_PLL3() that is now unused. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- .../drm/i915/display/intel_display_reg_defs.h | 1 - drivers/gpu/drm/i915/i915_reg.h | 59 +++++++++---------- 2 files changed, 29 insertions(+), 31 deletions(-)