| Message ID | 20221223180016.2068508-6-christoph.muellner@vrull.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for the T-Head vendor extensions | expand |
On Sat, Dec 24, 2022 at 4:01 AM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > From: Christoph Müllner <christoph.muellner@vrull.eu> > > This patch adds support for the XTheadBs ISA extension. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Split XtheadB* extension into individual commits > - Use single decoder for XThead extensions > > Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ > target/riscv/translate.c | 3 ++- > target/riscv/xthead.decode | 3 +++ > 5 files changed, 23 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b5285fb7a7..17273425a8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), > + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), > @@ -1066,6 +1067,7 @@ static Property riscv_cpu_extensions[] = { > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0ac1d3f5ef..5f68cb1e1e 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -467,6 +467,7 @@ struct RISCVCPUConfig { > /* Vendor-specific custom extensions */ > bool ext_xtheadba; > bool ext_xtheadbb; > + bool ext_xtheadbs; > bool ext_xtheadcmo; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc > index a55d1491fa..fb1f2c5731 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -28,6 +28,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADBS(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadbs) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADCMO(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > return false; \ > @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) > return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); > } > > +/* XTheadBs */ > + > +/* th.tst is an alternate encoding for bexti (from Zbs) */ > +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) > +{ > + REQUIRE_XTHEADBS(ctx); > + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); > +} > + > /* XTheadCmo */ > > static inline int priv_level(DisasContext *ctx) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8439ff0bf4..fc326e0a79 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -128,7 +128,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) > static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > { > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; > + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > + ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 8cd140891b..8494805611 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 > th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 > th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 > > +# XTheadBs > +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 > + > # XTheadCmo > th_dcache_call 0000000 00001 00000 000 00000 0001011 > th_dcache_ciall 0000000 00011 00000 000 00000 0001011 > -- > 2.38.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b5285fb7a7..17273425a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1066,6 +1067,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0ac1d3f5ef..5f68cb1e1e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -467,6 +467,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index a55d1491fa..fb1f2c5731 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -28,6 +28,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBS(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbs) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); } +/* XTheadBs */ + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + REQUIRE_XTHEADBS(ctx); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8439ff0bf4..fc326e0a79 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -128,7 +128,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8cd140891b..8494805611 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 +# XTheadBs +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011