| Message ID | 1675091494-13988-10-git-send-email-quic_vpolimer@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add PSR support for eDP | expand |
On 30/01/2023 17:11, Vinod Polimera wrote: > From: Sankeerth Billakanti <quic_sbillaka@quicinc.com> > > Updated frames get queued if self_refresh_aware is set when the > sink is in psr. To support bridge enable and avoid queuing of update > frames, reset the self_refresh_aware state after entering psr. > > Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++- > 1 file changed, 24 insertions(+), 1 deletion(-) As I stated in v11's discussion, I do not like the way this change plays with the self_refresh_aware. Please find another way to work around the timing issue (let's probably continue the discussion back in v11).
> -----Original Message----- > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Sent: Tuesday, January 31, 2023 6:19 PM > To: Vinod Polimera (QUIC) <quic_vpolimer@quicinc.com>; dri- > devel@lists.freedesktop.org; linux-arm-msm@vger.kernel.org; > freedreno@lists.freedesktop.org; devicetree@vger.kernel.org > Cc: Sankeerth Billakanti (QUIC) <quic_sbillaka@quicinc.com>; linux- > kernel@vger.kernel.org; robdclark@gmail.com; dianders@chromium.org; > swboyd@chromium.org; Kalyan Thota (QUIC) <quic_kalyant@quicinc.com>; > Kuogee Hsieh (QUIC) <quic_khsieh@quicinc.com>; Vishnuvardhan > Prodduturi (QUIC) <quic_vproddut@quicinc.com>; Bjorn Andersson (QUIC) > <quic_bjorande@quicinc.com>; Abhinav Kumar (QUIC) > <quic_abhinavk@quicinc.com> > Subject: Re: [PATCH v12 09/14] drm/msm/dp: disable self_refresh_aware > after entering psr > > On 30/01/2023 17:11, Vinod Polimera wrote: > > From: Sankeerth Billakanti <quic_sbillaka@quicinc.com> > > > > Updated frames get queued if self_refresh_aware is set when the > > sink is in psr. To support bridge enable and avoid queuing of update > > frames, reset the self_refresh_aware state after entering psr. > > > > Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> > > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > > --- > > drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++- > > 1 file changed, 24 insertions(+), 1 deletion(-) > > As I stated in v11's discussion, I do not like the way this change plays > with the self_refresh_aware. Please find another way to work around the > timing issue (let's probably continue the discussion back in v11). > Currently we are not able to reproduce the issue with KASAN enabled and minimum cpu frequency builds. We can revisit this patch if it is reproduced in future. Meanwhile I think on handling it in a different way. Can we not consider this patch for current merge? > -- > With best wishes > Dmitry Thanks, Vinod P.
On 07/02/2023 16:28, Vinod Polimera wrote: > > >> -----Original Message----- >> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Sent: Tuesday, January 31, 2023 6:19 PM >> To: Vinod Polimera (QUIC) <quic_vpolimer@quicinc.com>; dri- >> devel@lists.freedesktop.org; linux-arm-msm@vger.kernel.org; >> freedreno@lists.freedesktop.org; devicetree@vger.kernel.org >> Cc: Sankeerth Billakanti (QUIC) <quic_sbillaka@quicinc.com>; linux- >> kernel@vger.kernel.org; robdclark@gmail.com; dianders@chromium.org; >> swboyd@chromium.org; Kalyan Thota (QUIC) <quic_kalyant@quicinc.com>; >> Kuogee Hsieh (QUIC) <quic_khsieh@quicinc.com>; Vishnuvardhan >> Prodduturi (QUIC) <quic_vproddut@quicinc.com>; Bjorn Andersson (QUIC) >> <quic_bjorande@quicinc.com>; Abhinav Kumar (QUIC) >> <quic_abhinavk@quicinc.com> >> Subject: Re: [PATCH v12 09/14] drm/msm/dp: disable self_refresh_aware >> after entering psr Can we please get rid of this somehow? >> >> On 30/01/2023 17:11, Vinod Polimera wrote: >>> From: Sankeerth Billakanti <quic_sbillaka@quicinc.com> >>> >>> Updated frames get queued if self_refresh_aware is set when the >>> sink is in psr. To support bridge enable and avoid queuing of update >>> frames, reset the self_refresh_aware state after entering psr. >>> >>> Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> >>> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> >>> --- >>> drivers/gpu/drm/msm/dp/dp_drm.c | 25 ++++++++++++++++++++++++- >>> 1 file changed, 24 insertions(+), 1 deletion(-) >> >> As I stated in v11's discussion, I do not like the way this change plays >> with the self_refresh_aware. Please find another way to work around the >> timing issue (let's probably continue the discussion back in v11). >> > Currently we are not able to reproduce the issue with KASAN enabled and minimum cpu frequency builds. > We can revisit this patch if it is reproduced in future. Meanwhile I think on handling it in a different way. > Can we not consider this patch for current merge? Ack.
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 029e08c..01ca148b 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -134,6 +134,8 @@ static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, struct drm_crtc_state *old_crtc_state; struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->dp_display; + struct drm_connector *connector; + struct drm_connector_state *conn_state = NULL; /* * Check the old state of the crtc to determine if the panel @@ -150,10 +152,20 @@ static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, if (old_crtc_state && old_crtc_state->self_refresh_active) { dp_display_set_psr(dp, false); - return; + goto psr_aware; } dp_bridge_atomic_enable(drm_bridge, old_bridge_state); + +psr_aware: + connector = drm_atomic_get_new_connector_for_encoder(atomic_state, + drm_bridge->encoder); + if (connector) + conn_state = drm_atomic_get_new_connector_state(atomic_state, + connector); + + if (conn_state) + conn_state->self_refresh_aware = dp->psr_supported; } static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -164,6 +176,14 @@ static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL; struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->dp_display; + struct drm_connector *connector; + struct drm_connector_state *conn_state = NULL; + + connector = drm_atomic_get_old_connector_for_encoder(atomic_state, + drm_bridge->encoder); + if (connector) + conn_state = drm_atomic_get_new_connector_state(atomic_state, + connector); crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state, drm_bridge->encoder); @@ -190,6 +210,9 @@ static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, * when display disable occurs while the sink is in psr state. */ if (new_crtc_state->self_refresh_active) { + if (conn_state) + conn_state->self_refresh_aware = false; + dp_display_set_psr(dp, true); return; } else if (old_crtc_state->self_refresh_active) {