| Message ID | 20230209105628.50294-4-bchihi@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Daniel Lezcano |
| Headers | show |
| Series | Add LVTS Thermal Architecture | expand |
On 09/02/2023 11:56, bchihi@baylibre.com wrote: > From: Balsam CHIHI <bchihi@baylibre.com> > > Add efuse node. > This will be required by the thermal driver to get the calibration data. > > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Link: https://lore.kernel.org/r/20230124131717.128660-4-bchihi@baylibre.com > Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> This patch is already accepted [1], please drop it from your list. Regards, Matthias [1] https://lore.kernel.org/lkml/104bb37e-55c3-8dd0-f501-0e8a142511e6@gmail.com/ > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 5d31536f4c486..09df105f4606d 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { > dp_calibration: dp-data@1ac { > reg = <0x1ac 0x10>; > }; > + lvts_efuse_data1: lvts1-calib@1bc { > + reg = <0x1bc 0x14>; > + }; > + lvts_efuse_data2: lvts2-calib@1d0 { > + reg = <0x1d0 0x38>; > + }; > }; > > u3phy2: t-phy@11c40000 {
Hi Matthias, On Thu, Feb 9, 2023 at 5:28 PM Matthias Brugger <matthias.bgg@gmail.com> wrote: > > > > On 09/02/2023 11:56, bchihi@baylibre.com wrote: > > From: Balsam CHIHI <bchihi@baylibre.com> > > > > Add efuse node. > > This will be required by the thermal driver to get the calibration data. > > > > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Link: https://lore.kernel.org/r/20230124131717.128660-4-bchihi@baylibre.com > > Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> > > This patch is already accepted [1], please drop it from your list. Yes sure. I will. Thank you. > > Regards, > Matthias > > [1] https://lore.kernel.org/lkml/104bb37e-55c3-8dd0-f501-0e8a142511e6@gmail.com/ > > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > index 5d31536f4c486..09df105f4606d 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > > @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { > > dp_calibration: dp-data@1ac { > > reg = <0x1ac 0x10>; > > }; > > + lvts_efuse_data1: lvts1-calib@1bc { > > + reg = <0x1bc 0x14>; > > + }; > > + lvts_efuse_data2: lvts2-calib@1d0 { > > + reg = <0x1d0 0x38>; > > + }; > > }; > > > > u3phy2: t-phy@11c40000 { Best regards, Balsam
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c486..09df105f4606d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { dp_calibration: dp-data@1ac { reg = <0x1ac 0x10>; }; + lvts_efuse_data1: lvts1-calib@1bc { + reg = <0x1bc 0x14>; + }; + lvts_efuse_data2: lvts2-calib@1d0 { + reg = <0x1d0 0x38>; + }; }; u3phy2: t-phy@11c40000 {