| Message ID | 20230209232228.859317-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/xehp: LNCF/LBCF workarounds should be on the GT list | expand |
On Thu, Feb 09, 2023 at 03:22:28PM -0800, Matt Roper wrote: > Although registers in the L3 bank/node configuration ranges are marked > as having "DEV" reset characteristics in the bspec, this appears to be a > hold-over from pre-Xe_HP platforms. In reality, these registers > maintain their values across engine resets, meaning that workarounds > and tuning settings targetting them should be placed on the GT > workaround list rather than an engine workaround list. > > Note that an extra clue here is that these registers moved from the > RENDER forcewake domain to the GT forcewake domain in Xe_HP; generally > RCS/CCS engine resets should not lead to the reset of a register that > lives outside the RENDER domain. > > Re-applying these registers on engine resets wouldn't actually hurt > anything, but is unnecessary and just makes it more confusing to anyone > trying to decipher how these registers really work. > > v2: > - Also move DG2's Wa_14010648519 to the GT list. (Gustavo) > > Cc: Gustavo Sousa <gustavo.sousa@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 70 ++++++++++++--------- > 1 file changed, 42 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 8859eb118510..989e9578e122 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1499,6 +1499,12 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_1409757795:xehpsdv */ > wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); > > + /* Wa_18011725039:xehpsdv */ > + if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { > + wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); > + wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); > + } > + > /* Wa_16011155590:xehpsdv */ > if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > @@ -1548,6 +1554,9 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_14014368820:xehpsdv */ > wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, > INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); > + > + /* Wa_14010670810:xehpsdv */ > + wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); > } > > static void > @@ -1669,6 +1678,9 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_1509235366:dg2 */ > wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, > INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); > + > + /* Wa_14010648519:dg2 */ > + wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); > } > > static void > @@ -1684,6 +1696,9 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); > wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); > wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); > + > + /* Wa_16016694945 */ > + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); > } > > static void > @@ -1724,11 +1739,36 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > debug_dump_steering(gt); > } > > +/* > + * The bspec performance guide has recommended MMIO tuning settings. These > + * aren't truly "workarounds" but we want to program them through the > + * workaround infrastructure to make sure they're (re)applied at the proper > + * times. > + * > + * The settings in this function are for settings that persist through > + * engine resets and also are not part of any engine's register state context. > + * I.e., settings that only need to be re-applied in the event of a full GT > + * reset. > + */ > +static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) > +{ > + if (IS_PONTEVECCHIO(gt->i915)) { > + wa_mcr_write(wal, XEHPC_L3SCRUB, > + SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); > + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); > + } > + > + if (IS_DG2(gt->i915)) > + wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); > +} > + > static void > gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) > { > struct drm_i915_private *i915 = gt->i915; > > + gt_tuning_settings(gt, wal); > + > if (gt->type == GT_MEDIA) { > if (MEDIA_VER(i915) >= 13) > xelpmp_gt_workarounds_init(gt, wal); > @@ -2403,16 +2443,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); > } > > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) > /* Wa_22010430635:dg2 */ > wa_mcr_masked_en(wal, > GEN9_ROW_CHICKEN4, > GEN12_DISABLE_GRF_CLEAR); > > - /* Wa_14010648519:dg2 */ > - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); > - } > - > /* Wa_14013202645:dg2 */ > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || > IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) > @@ -2897,16 +2933,8 @@ static void > add_render_compute_tuning_settings(struct drm_i915_private *i915, > struct i915_wa_list *wal) > { > - if (IS_PONTEVECCHIO(i915)) { > - wa_mcr_write(wal, XEHPC_L3SCRUB, > - SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); > - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); > - } > - > - if (IS_DG2(i915)) { > - wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); > + if (IS_DG2(i915)) > wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); > - } > > /* > * This tuning setting proves beneficial only on ATS-M designs; the > @@ -2988,11 +3016,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > 0, false); > } > > - if (IS_PONTEVECCHIO(i915)) { > - /* Wa_16016694945 */ > - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); > - } > - > if (IS_XEHPSDV(i915)) { > /* Wa_1409954639 */ > wa_mcr_masked_en(wal, > @@ -3004,18 +3027,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > GEN9_ROW_CHICKEN4, > GEN12_DISABLE_GRF_CLEAR); > > - /* Wa_14010670810:xehpsdv */ > - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); > - > /* Wa_14010449647:xehpsdv */ > wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); > - > - /* Wa_18011725039:xehpsdv */ > - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { > - wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); > - wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); > - } > } > > if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { > -- > 2.39.1 >
On Fri, Feb 10, 2023 at 06:21:06PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/xehp: LNCF/LBCF workarounds should be on the GT list > URL : https://patchwork.freedesktop.org/series/113857/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_12722_full -> Patchwork_113857v1_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Applied to drm-intel-gt-next. Thanks Gustavo for the review. Matt > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/index.html > > Participating hosts (10 -> 10) > ------------------------------ > > Additional (1): shard-rkl0 > Missing (1): shard-tglu-9 > > Known issues > ------------ > > Here are the changes found in Patchwork_113857v1_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_fair@basic-pace-share@rcs0: > - shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html > > * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: > - shard-glk: [PASS][3] -> [FAIL][4] ([i915#72]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html > > * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1: > - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +23 similar issues > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-snb4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1.html > > > #### Possible fixes #### > > * igt@api_intel_bb@object-reloc-keep-cache: > - {shard-rkl}: [SKIP][6] ([i915#3281]) -> [PASS][7] +7 similar issues > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-3/igt@api_intel_bb@object-reloc-keep-cache.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html > > * igt@drm_fdinfo@idle@rcs0: > - {shard-rkl}: [FAIL][8] ([i915#7742]) -> [PASS][9] > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-3/igt@drm_fdinfo@idle@rcs0.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html > > * igt@drm_read@invalid-buffer: > - {shard-tglu}: [SKIP][10] ([i915#1845]) -> [PASS][11] +1 similar issue > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-tglu-6/igt@drm_read@invalid-buffer.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-tglu-8/igt@drm_read@invalid-buffer.html > > * igt@fbdev@eof: > - {shard-rkl}: [SKIP][12] ([i915#2582]) -> [PASS][13] +1 similar issue > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-1/igt@fbdev@eof.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@fbdev@eof.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - {shard-rkl}: [FAIL][14] ([i915#2842]) -> [PASS][15] +1 similar issue > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-1/igt@gem_exec_fair@basic-none-rrul@rcs0.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@gem_exec_fair@basic-none-rrul@rcs0.html > > * igt@gem_exec_flush@basic-batch-kernel-default-cmd: > - {shard-rkl}: [SKIP][16] ([fdo#109313]) -> [PASS][17] > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html > > * igt@gem_partial_pwrite_pread@writes-after-reads: > - {shard-rkl}: [SKIP][18] ([i915#3282]) -> [PASS][19] +6 similar issues > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads.html > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads.html > > * igt@gen9_exec_parse@batch-without-end: > - {shard-rkl}: [SKIP][20] ([i915#2527]) -> [PASS][21] +3 similar issues > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-3/igt@gen9_exec_parse@batch-without-end.html > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@gen9_exec_parse@batch-without-end.html > > * igt@i915_pm_rpm@drm-resources-equal: > - {shard-tglu}: [SKIP][22] ([i915#3547]) -> [PASS][23] > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-tglu-6/igt@i915_pm_rpm@drm-resources-equal.html > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-tglu-8/igt@i915_pm_rpm@drm-resources-equal.html > > * igt@i915_pm_rpm@modeset-lpsp: > - {shard-rkl}: [SKIP][24] ([i915#1397]) -> [PASS][25] > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-5/igt@i915_pm_rpm@modeset-lpsp.html > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html > > * igt@i915_pm_sseu@full-enable: > - {shard-rkl}: [SKIP][26] ([i915#4387]) -> [PASS][27] > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-3/igt@i915_pm_sseu@full-enable.html > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-5/igt@i915_pm_sseu@full-enable.html > > * igt@i915_suspend@basic-s3-without-i915: > - {shard-rkl}: [FAIL][28] ([fdo#103375]) -> [PASS][29] > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html > > * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs: > - {shard-rkl}: [SKIP][30] ([i915#1845] / [i915#4098]) -> [PASS][31] +19 similar issues > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html > > * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: > - {shard-tglu}: [SKIP][32] ([i915#7651]) -> [PASS][33] +7 similar issues > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-tglu-6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-tglu-8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html > > * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions: > - shard-glk: [FAIL][34] ([i915#2346]) -> [PASS][35] > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - {shard-rkl}: [SKIP][36] ([i915#1849] / [i915#4098]) -> [PASS][37] +9 similar issues > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu: > - {shard-tglu}: [SKIP][38] ([i915#1849]) -> [PASS][39] > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html > > * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move: > - shard-snb: [SKIP][40] ([fdo#109271]) -> [PASS][41] > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html > > * igt@kms_plane@plane-panning-bottom-right@pipe-a-planes: > - {shard-tglu}: [SKIP][42] ([i915#1849] / [i915#3558]) -> [PASS][43] +1 similar issue > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-tglu-6/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-tglu-8/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html > > * igt@kms_plane@plane-position-covered@pipe-a-planes: > - {shard-rkl}: [SKIP][44] ([i915#1849]) -> [PASS][45] +2 similar issues > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-1/igt@kms_plane@plane-position-covered@pipe-a-planes.html > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@kms_plane@plane-position-covered@pipe-a-planes.html > > * igt@kms_psr@primary_render: > - {shard-rkl}: [SKIP][46] ([i915#1072]) -> [PASS][47] > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-5/igt@kms_psr@primary_render.html > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@kms_psr@primary_render.html > > * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a: > - {shard-rkl}: [SKIP][48] ([i915#4070] / [i915#4098]) -> [PASS][49] > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-rkl-1/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a.html > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a.html > > * igt@kms_vblank@pipe-b-wait-idle: > - {shard-tglu}: [SKIP][50] ([i915#1845] / [i915#7651]) -> [PASS][51] +3 similar issues > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12722/shard-tglu-6/igt@kms_vblank@pipe-b-wait-idle.html > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/shard-tglu-8/igt@kms_vblank@pipe-b-wait-idle.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 > [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 > [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 > [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 > [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 > [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 > [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 > [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 > [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 > [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 > [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 > [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 > [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 > [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 > [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 > [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 > [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 > [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 > [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 > [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 > [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 > [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 > [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 > [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 > [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 > [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 > [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 > [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 > [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 > [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 > [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 > [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937 > [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 > [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 > [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 > [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 > [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 > [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 > [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 > [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 > [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 > [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 > [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 > [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 > [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 > [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 > [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 > [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 > [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 > [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 > [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 > [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 > [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 > [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 > [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 > [i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 > [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 > [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 > [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 > [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 > [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 > [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 > [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 > [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 > [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 > [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 > [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 > [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 > [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 > [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884 > [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 > [i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 > [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 > [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 > [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 > [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230 > [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245 > [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 > [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 > [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 > [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 > [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493 > [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 > [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590 > [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 > [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 > [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 > [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 > [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953 > [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037 > [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052 > [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 > [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 > [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 > [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 > [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582 > [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651 > [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 > [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701 > [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 > [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 > [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 > [i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949 > [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957 > [i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984 > > > Build changes > ------------- > > * Linux: CI_DRM_12722 -> Patchwork_113857v1 > > CI-20190529: 20190529 > CI_DRM_12722: ec3cb908765a89bf72518590473c464a543372ff @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_7155: 75c508d4e19c65683d4060cb3a772df600aaf23e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_113857v1: ec3cb908765a89bf72518590473c464a543372ff @ git://anongit.freedesktop.org/gfx-ci/linux > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113857v1/index.html
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 8859eb118510..989e9578e122 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1499,6 +1499,12 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_1409757795:xehpsdv */ wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); + /* Wa_18011725039:xehpsdv */ + if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { + wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); + wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); + } + /* Wa_16011155590:xehpsdv */ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, @@ -1548,6 +1554,9 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14014368820:xehpsdv */ wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); + + /* Wa_14010670810:xehpsdv */ + wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); } static void @@ -1669,6 +1678,9 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_1509235366:dg2 */ wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); + + /* Wa_14010648519:dg2 */ + wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); } static void @@ -1684,6 +1696,9 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); + + /* Wa_16016694945 */ + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); } static void @@ -1724,11 +1739,36 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) debug_dump_steering(gt); } +/* + * The bspec performance guide has recommended MMIO tuning settings. These + * aren't truly "workarounds" but we want to program them through the + * workaround infrastructure to make sure they're (re)applied at the proper + * times. + * + * The settings in this function are for settings that persist through + * engine resets and also are not part of any engine's register state context. + * I.e., settings that only need to be re-applied in the event of a full GT + * reset. + */ +static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) +{ + if (IS_PONTEVECCHIO(gt->i915)) { + wa_mcr_write(wal, XEHPC_L3SCRUB, + SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); + } + + if (IS_DG2(gt->i915)) + wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); +} + static void gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) { struct drm_i915_private *i915 = gt->i915; + gt_tuning_settings(gt, wal); + if (gt->type == GT_MEDIA) { if (MEDIA_VER(i915) >= 13) xelpmp_gt_workarounds_init(gt, wal); @@ -2403,16 +2443,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); } - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) /* Wa_22010430635:dg2 */ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_GRF_CLEAR); - /* Wa_14010648519:dg2 */ - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); - } - /* Wa_14013202645:dg2 */ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) @@ -2897,16 +2933,8 @@ static void add_render_compute_tuning_settings(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_PONTEVECCHIO(i915)) { - wa_mcr_write(wal, XEHPC_L3SCRUB, - SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); - } - - if (IS_DG2(i915)) { - wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); + if (IS_DG2(i915)) wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); - } /* * This tuning setting proves beneficial only on ATS-M designs; the @@ -2988,11 +3016,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 0, false); } - if (IS_PONTEVECCHIO(i915)) { - /* Wa_16016694945 */ - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); - } - if (IS_XEHPSDV(i915)) { /* Wa_1409954639 */ wa_mcr_masked_en(wal, @@ -3004,18 +3027,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li GEN9_ROW_CHICKEN4, GEN12_DISABLE_GRF_CLEAR); - /* Wa_14010670810:xehpsdv */ - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); - /* Wa_14010449647:xehpsdv */ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); - - /* Wa_18011725039:xehpsdv */ - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { - wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); - wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); - } } if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
Although registers in the L3 bank/node configuration ranges are marked as having "DEV" reset characteristics in the bspec, this appears to be a hold-over from pre-Xe_HP platforms. In reality, these registers maintain their values across engine resets, meaning that workarounds and tuning settings targetting them should be placed on the GT workaround list rather than an engine workaround list. Note that an extra clue here is that these registers moved from the RENDER forcewake domain to the GT forcewake domain in Xe_HP; generally RCS/CCS engine resets should not lead to the reset of a register that lives outside the RENDER domain. Re-applying these registers on engine resets wouldn't actually hurt anything, but is unnecessary and just makes it more confusing to anyone trying to decipher how these registers really work. v2: - Also move DG2's Wa_14010648519 to the GT list. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 70 ++++++++++++--------- 1 file changed, 42 insertions(+), 28 deletions(-)