| Message ID | 20230213180215.1524938-16-bmeng@tinylab.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Various fixes to gdbstub and CSR access | expand |
On 2023/2/14 12:12, Bin Meng wrote: > At present with a debugger attached sstc CSRs can only be accssed > when CPU is in M-mode, or configured correctly. > > Fix it by adjusting their predicate() routine logic so that the > static config check comes before the run-time check, as well as > addding a debugger check. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> Similar typo, otherwise Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > --- > > target/riscv/csr.c | 19 ++++++++++++++----- > 1 file changed, 14 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d6bcb7f275..c6a7745cb2 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -951,6 +951,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno) > return RISCV_EXCP_ILLEGAL_INST; > } > > + if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { > + hmode_check = true; > + } > + > + RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > + > + if (env->debugger) { > + return RISCV_EXCP_NONE; > + } > + > if (env->priv == PRV_M) { > return RISCV_EXCP_NONE; > } > @@ -971,11 +984,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) > } > } > > - if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { > - hmode_check = true; > - } > - > - return hmode_check ? hmode(env, csrno) : smode(env, csrno); > + return RISCV_EXCP_NONE; > } > > static RISCVException sstc_32(CPURISCVState *env, int csrno)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d6bcb7f275..c6a7745cb2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -951,6 +951,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { + hmode_check = true; + } + + RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + if (env->debugger) { + return RISCV_EXCP_NONE; + } + if (env->priv == PRV_M) { return RISCV_EXCP_NONE; } @@ -971,11 +984,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) } } - if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { - hmode_check = true; - } - - return hmode_check ? hmode(env, csrno) : smode(env, csrno); + return RISCV_EXCP_NONE; } static RISCVException sstc_32(CPURISCVState *env, int csrno)
At present with a debugger attached sstc CSRs can only be accssed when CPU is in M-mode, or configured correctly. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as addding a debugger check. Signed-off-by: Bin Meng <bmeng@tinylab.org> --- target/riscv/csr.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-)