| Message ID | 20230214083833.44205-7-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Some updates to float point related extensions | expand |
On 2/14/23 05:38, Weiwei Li wrote: > Add check for Zvfh and Zvfhmin > Nit: Missing period in the end. > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4797ef9c42..8fe76707a0 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + if (cpu->cfg.ext_zvfh) { > + cpu->cfg.ext_zvfhmin = true; > + } > + > + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { > + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); > + return; > + } > + > + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { > + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); > + return; > + } > + > /* Set the ISA extensions, checks should have happened above */ > if (cpu->cfg.ext_zhinx) { > cpu->cfg.ext_zhinxmin = true;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4797ef9c42..8fe76707a0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvfh) { + cpu->cfg.ext_zvfhmin = true; + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { cpu->cfg.ext_zhinxmin = true;