| Message ID | 20230210133635.589647-5-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | enable write_misa() and RISCV_FEATURE_* cleanups | expand |
On 2023/2/10 21:36, Daniel Henrique Barboza wrote: > We're going to do changes that requires accessing the RISCVCPUConfig > struct from the RISCVCPU, having access only to a CPURISCVState 'env' > pointer. Add a helper to make the code easier to read. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > --- > target/riscv/cpu.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6509ffa951..00a464c9c4 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) > #endif > #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) > > +static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env) > +{ > + return env_archcpu(env)->cfg; > +} > + > #if defined(TARGET_RISCV32) > #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) > #else
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6509ffa951..00a464c9c4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) +static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env) +{ + return env_archcpu(env)->cfg; +} + #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else
We're going to do changes that requires accessing the RISCVCPUConfig struct from the RISCVCPU, having access only to a CPURISCVState 'env' pointer. Add a helper to make the code easier to read. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.h | 5 +++++ 1 file changed, 5 insertions(+)