| Message ID | 20230215205911.695745-5-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Add support for Zicbo[m,z,p] instructions | expand |
On 2/15/23 10:59, Daniel Henrique Barboza wrote: > From: Christoph Muellner<cmuellner@linux.com> > > The cmo.prefetch instructions are nops for QEMU (no emulation of the > memory hierarchy, no illegal instructions, no permission faults, no > traps). > > Add a comment noting where they would be decoded in case cbo.prefetch > instructions become relevant in the future. > > Co-developed-by: Philipp Tomsich<philipp.tomsich@vrull.eu> > Signed-off-by: Christoph Muellner<cmuellner@linux.com> > Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com> > --- > target/riscv/insn32.decode | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3788f86528..1aebd37572 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -134,6 +134,7 @@ addi ............ ..... 000 ..... 0010011 @i slti ............ ..... 010 ..... 0010011 @i sltiu ............ ..... 011 ..... 0010011 @i xori ............ ..... 100 ..... 0010011 @i +# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded. ori ............ ..... 110 ..... 0010011 @i andi ............ ..... 111 ..... 0010011 @i slli 00000. ...... ..... 001 ..... 0010011 @sh