| Message ID | 20230215041257.14548-5-tinghan.shen@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for MT8195 SCP 2nd core | expand |
On 15/02/2023 05:12, Tinghan Shen wrote: > Add MT8195 SCP core 1 related register definitions. > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> In general I would say this patch should be squashed into 5/12, but please see comments below. > --- > drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h > index ea6fa1100a00..3778894c96f3 100644 > --- a/drivers/remoteproc/mtk_common.h > +++ b/drivers/remoteproc/mtk_common.h > @@ -47,6 +47,7 @@ > #define MT8192_SCP2SPM_IPC_CLR 0x4094 > #define MT8192_GIPC_IN_SET 0x4098 > #define MT8192_HOST_IPC_INT_BIT BIT(0) > +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) > > #define MT8192_CORE0_SW_RSTN_CLR 0x10000 > #define MT8192_CORE0_SW_RSTN_SET 0x10004 > @@ -56,6 +57,26 @@ > > #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) > > +#define MT8195_CPU1_SRAM_PD 0x1084 > +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 > +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C > +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 > +#define MT8195_CORE1_SW_RSTN_SET 0x20004 > +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 > +#define MT8195_CORE1_WDT_IRQ 0x20030 Should be part of 10/12 maybe? > +#define MT8195_CORE1_WDT_CFG 0x20034 > + > +#define MT8195_SEC_CTRL 0x85000 > +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) > +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) > +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 > +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 > +#define MT8195_L2TCM_OFFSET 0x850d0 Should be part of 9/12 maybe > +#define SCP_SRAM_REMAP_LOW 0 > +#define SCP_SRAM_REMAP_HIGH 1 > +#define SCP_SRAM_REMAP_OFFSET 2 > +#define SCP_SRAM_REMAP_SIZE 3 Never used. > + > #define SCP_FW_VER_LEN 32 > #define SCP_SHARE_BUFFER_SIZE 288 >
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..3778894c96f3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -56,6 +57,26 @@ #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 +#define MT8195_CORE1_WDT_CFG 0x20034 + +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 +#define SCP_SRAM_REMAP_LOW 0 +#define SCP_SRAM_REMAP_HIGH 1 +#define SCP_SRAM_REMAP_OFFSET 2 +#define SCP_SRAM_REMAP_SIZE 3 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288