diff mbox series

[v5,34/54] clk: mediatek: mt7986-eth: Migrate to common probe mechanism

Message ID 20230222092543.19187-35-angelogioacchino.delregno@collabora.com (mailing list archive)
State Superseded, archived
Headers show
Series MediaTek clocks: full module build and cleanups | expand

Commit Message

AngeloGioacchino Del Regno Feb. 22, 2023, 9:25 a.m. UTC 
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also remove __initconst annotations (as these structures
are used also at runtime).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
---
 drivers/clk/mediatek/clk-mt7986-eth.c | 83 +++++++++++----------------
 1 file changed, 32 insertions(+), 51 deletions(-)

Comments

Daniel Golle Feb. 22, 2023, 6:02 p.m. UTC | #1 
On Wed, Feb 22, 2023 at 10:25:23AM +0100, AngeloGioacchino Del Regno wrote:
> Convert this driver to use the common mtk_clk_simple_probe() mechanism.
> While at it, also remove __initconst annotations (as these structures
> are used also at runtime).
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Tested-by: Daniel Golle <daniel@makrotopia.org>
(on BananaPi BPi-R3)

> ---
>  drivers/clk/mediatek/clk-mt7986-eth.c | 83 +++++++++++----------------
>  1 file changed, 32 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c
> index e04bc6845ea6..138ba0a47221 100644
> --- a/drivers/clk/mediatek/clk-mt7986-eth.c
> +++ b/drivers/clk/mediatek/clk-mt7986-eth.c
> @@ -25,7 +25,7 @@ static const struct mtk_gate_regs sgmii0_cg_regs = {
>  #define GATE_SGMII0(_id, _name, _parent, _shift)		\
>  	GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
>  
> -static const struct mtk_gate sgmii0_clks[] __initconst = {
> +static const struct mtk_gate sgmii0_clks[] = {
>  	GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
>  	GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
>  	GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
> @@ -41,7 +41,7 @@ static const struct mtk_gate_regs sgmii1_cg_regs = {
>  #define GATE_SGMII1(_id, _name, _parent, _shift)		\
>  	GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
>  
> -static const struct mtk_gate sgmii1_clks[] __initconst = {
> +static const struct mtk_gate sgmii1_clks[] = {
>  	GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
>  	GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
>  	GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
> @@ -57,7 +57,7 @@ static const struct mtk_gate_regs eth_cg_regs = {
>  #define GATE_ETH(_id, _name, _parent, _shift)			\
>  	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
>  
> -static const struct mtk_gate eth_clks[] __initconst = {
> +static const struct mtk_gate eth_clks[] = {
>  	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
>  	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
>  	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
> @@ -65,56 +65,37 @@ static const struct mtk_gate eth_clks[] __initconst = {
>  	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
>  };
>  
> -static void __init mtk_sgmiisys_0_init(struct device_node *node)
> -{
> -	struct clk_hw_onecell_data *clk_data;
> -	int r;
> -
> -	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
> -
> -	mtk_clk_register_gates(NULL, node, sgmii0_clks,
> -			       ARRAY_SIZE(sgmii0_clks), clk_data);
> -
> -	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> -	if (r)
> -		pr_err("%s(): could not register clock provider: %d\n",
> -		       __func__, r);
> -}
> -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
> -	       mtk_sgmiisys_0_init);
> -
> -static void __init mtk_sgmiisys_1_init(struct device_node *node)
> -{
> -	struct clk_hw_onecell_data *clk_data;
> -	int r;
> -
> -	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
> -
> -	mtk_clk_register_gates(NULL, node, sgmii1_clks,
> -			       ARRAY_SIZE(sgmii1_clks), clk_data);
> -
> -	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> -
> -	if (r)
> -		pr_err("%s(): could not register clock provider: %d\n",
> -		       __func__, r);
> -}
> -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
> -	       mtk_sgmiisys_1_init);
> +static const struct mtk_clk_desc eth_desc = {
> +	.clks = eth_clks,
> +	.num_clks = ARRAY_SIZE(eth_clks),
> +};
>  
> -static void __init mtk_ethsys_init(struct device_node *node)
> -{
> -	struct clk_hw_onecell_data *clk_data;
> -	int r;
> +static const struct mtk_clk_desc sgmii0_desc = {
> +	.clks = sgmii0_clks,
> +	.num_clks = ARRAY_SIZE(sgmii0_clks),
> +};
>  
> -	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
> +static const struct mtk_clk_desc sgmii1_desc = {
> +	.clks = sgmii1_clks,
> +	.num_clks = ARRAY_SIZE(sgmii1_clks),
> +};
>  
> -	mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
> +static const struct of_device_id of_match_clk_mt7986_eth[] = {
> +	{ .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
> +	{ .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc },
> +	{ .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc },
> +	{ /* sentinel */ }
> +};
>  
> -	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> +static struct platform_driver clk_mt7986_eth_drv = {
> +	.driver = {
> +		.name = "clk-mt7986-eth",
> +		.of_match_table = of_match_clk_mt7986_eth,
> +	},
> +	.probe = mtk_clk_simple_probe,
> +	.remove = mtk_clk_simple_remove,
> +};
> +module_platform_driver(clk_mt7986_eth_drv);
>  
> -	if (r)
> -		pr_err("%s(): could not register clock provider: %d\n",
> -		       __func__, r);
> -}
> -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
> +MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver");
> +MODULE_LICENSE("GPL");
> -- 
> 2.39.2
> 
>
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c
index e04bc6845ea6..138ba0a47221 100644
--- a/drivers/clk/mediatek/clk-mt7986-eth.c
+++ b/drivers/clk/mediatek/clk-mt7986-eth.c
@@ -25,7 +25,7 @@  static const struct mtk_gate_regs sgmii0_cg_regs = {
 #define GATE_SGMII0(_id, _name, _parent, _shift)		\
 	GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 
-static const struct mtk_gate sgmii0_clks[] __initconst = {
+static const struct mtk_gate sgmii0_clks[] = {
 	GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
 	GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
 	GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
@@ -41,7 +41,7 @@  static const struct mtk_gate_regs sgmii1_cg_regs = {
 #define GATE_SGMII1(_id, _name, _parent, _shift)		\
 	GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 
-static const struct mtk_gate sgmii1_clks[] __initconst = {
+static const struct mtk_gate sgmii1_clks[] = {
 	GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
 	GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
 	GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
@@ -57,7 +57,7 @@  static const struct mtk_gate_regs eth_cg_regs = {
 #define GATE_ETH(_id, _name, _parent, _shift)			\
 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 
-static const struct mtk_gate eth_clks[] __initconst = {
+static const struct mtk_gate eth_clks[] = {
 	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
@@ -65,56 +65,37 @@  static const struct mtk_gate eth_clks[] __initconst = {
 	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
 };
 
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
-	struct clk_hw_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-	mtk_clk_register_gates(NULL, node, sgmii0_clks,
-			       ARRAY_SIZE(sgmii0_clks), clk_data);
-
-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
-	       mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
-	struct clk_hw_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-	mtk_clk_register_gates(NULL, node, sgmii1_clks,
-			       ARRAY_SIZE(sgmii1_clks), clk_data);
-
-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
-	       mtk_sgmiisys_1_init);
+static const struct mtk_clk_desc eth_desc = {
+	.clks = eth_clks,
+	.num_clks = ARRAY_SIZE(eth_clks),
+};
 
-static void __init mtk_ethsys_init(struct device_node *node)
-{
-	struct clk_hw_onecell_data *clk_data;
-	int r;
+static const struct mtk_clk_desc sgmii0_desc = {
+	.clks = sgmii0_clks,
+	.num_clks = ARRAY_SIZE(sgmii0_clks),
+};
 
-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
+static const struct mtk_clk_desc sgmii1_desc = {
+	.clks = sgmii1_clks,
+	.num_clks = ARRAY_SIZE(sgmii1_clks),
+};
 
-	mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+static const struct of_device_id of_match_clk_mt7986_eth[] = {
+	{ .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
+	{ .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc },
+	{ .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc },
+	{ /* sentinel */ }
+};
 
-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+static struct platform_driver clk_mt7986_eth_drv = {
+	.driver = {
+		.name = "clk-mt7986-eth",
+		.of_match_table = of_match_clk_mt7986_eth,
+	},
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+};
+module_platform_driver(clk_mt7986_eth_drv);
 
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-		       __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
+MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver");
+MODULE_LICENSE("GPL");