| Message ID | 20230224040852.37109-6-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add support for Svadu extension | expand |
On 2/24/23 01:08, Weiwei Li wrote: > When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled > during single-stage address translation. When the hypervisor extension is > implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is > enabled during G-stage address translation. > > Set *envcfg.HADE default true for backward compatibility. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 6 ++++-- > target/riscv/cpu_helper.c | 6 ++++++ > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 2d99679f2f..b81ab65de5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj) > env->bins = 0; > env->two_stage_lookup = false; > > - env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0); > - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0); > + env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | > + (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); > + env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | > + (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); > > /* Initialized default priorities of local interrupts. */ > for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 552c0f0b58..9e122ee92a 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -937,9 +937,11 @@ restart: > } > > bool pbmte = env->menvcfg & MENVCFG_PBMTE; > + bool hade = env->menvcfg & MENVCFG_HADE; > > if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { > pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); > + hade = hade && (env->henvcfg & HENVCFG_HADE); > } > > if (riscv_cpu_sxl(env) == MXL_RV32) { > @@ -998,6 +1000,10 @@ restart: > > /* Page table updates need to be atomic with MTTCG enabled */ > if (updated_pte != pte) { > + if (!hade) { > + return TRANSLATE_FAIL; > + } > + > /* > * - if accessed or dirty bits need updating, and the PTE is > * in RAM, then we do so atomically with a compare and swap.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2d99679f2f..b81ab65de5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj) env->bins = 0; env->two_stage_lookup = false; - env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0); - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0); + env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | + (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); + env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | + (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 552c0f0b58..9e122ee92a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -937,9 +937,11 @@ restart: } bool pbmte = env->menvcfg & MENVCFG_PBMTE; + bool hade = env->menvcfg & MENVCFG_HADE; if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); + hade = hade && (env->henvcfg & HENVCFG_HADE); } if (riscv_cpu_sxl(env) == MXL_RV32) { @@ -998,6 +1000,10 @@ restart: /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte != pte) { + if (!hade) { + return TRANSLATE_FAIL; + } + /* * - if accessed or dirty bits need updating, and the PTE is * in RAM, then we do so atomically with a compare and swap.