| Message ID | 20230224102438.6541-7-r-gunasekaran@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: j721s2: Add support for additional IPs | expand |
On 24/02/2023 11:24, Ravi Gunasekaran wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a > QSPI NOR flash on the common processor board connected to the OSPI1 > instance. Add support for the same > > Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > Changes from v10: > * Removed Link tag from commit message > > Changes from v9: > * Enabled fss and ospi nodes > > Changes from v8: > * No change > > Changes from v7: > * No change > > Changes from v6: > * No change > > Changes from v5: > * Removed Cc tags from commit message > > Changes from v4: > * No change > > Changes from v3: > * No change > > Changes from v2: > * No change > > Changes from v1: > * No change > > .../dts/ti/k3-j721s2-common-proc-board.dts | 39 +++++++++++++++++ > arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++++++++++++++++ > 2 files changed, 82 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > index fa38940fe6cd..76b420379645 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > @@ -206,6 +206,20 @@ > J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ > >; > }; > + > + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { > + pinctrl-single,pins = < > + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ > + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ > + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ > + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ > + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ > + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ > + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ > + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ > + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ > + >; > + }; > }; > > &main_gpio2 { > @@ -347,6 +361,31 @@ > maximum-speed = "high-speed"; > }; > > +&fss { > + status = "okay"; Where is the pinmux usage you said is required for the bus? > +}; > + > +&ospi1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; > + > + flash@0{ > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <40000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <2>; > + #address-cells = <1>; > + #size-cells = <1>; Are you sure these are correct? Aren't they marked as deprecated? Best regards, Krzysztof
On 24/02/23 4:41 pm, Krzysztof Kozlowski wrote: > On 24/02/2023 11:24, Ravi Gunasekaran wrote: >> From: Aswath Govindraju <a-govindraju@ti.com> >> >> J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a >> QSPI NOR flash on the common processor board connected to the OSPI1 >> instance. Add support for the same >> >> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> >> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> >> Signed-off-by: Matt Ranostay <mranostay@ti.com> >> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >> --- >> Changes from v10: >> * Removed Link tag from commit message >> [...] >> >> .../dts/ti/k3-j721s2-common-proc-board.dts | 39 +++++++++++++++++ >> arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++++++++++++++++ >> 2 files changed, 82 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> index fa38940fe6cd..76b420379645 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> @@ -206,6 +206,20 @@ >> J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >> >; >> }; >> + >> + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { >> + pinctrl-single,pins = < >> + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ >> + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ >> + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ >> + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ >> + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ >> + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ >> + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ >> + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ >> + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >> + >; >> + }; >> }; >> >> &main_gpio2 { >> @@ -347,6 +361,31 @@ >> maximum-speed = "high-speed"; >> }; >> >> +&fss { >> + status = "okay"; > > Where is the pinmux usage you said is required for the bus? Will remove the comment in [3/8] in the next series. > >> +}; >> + >> +&ospi1 { >> + status = "okay"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; >> + >> + flash@0{ >> + compatible = "jedec,spi-nor"; >> + reg = <0x0>; >> + spi-tx-bus-width = <1>; >> + spi-rx-bus-width = <4>; >> + spi-max-frequency = <40000000>; >> + cdns,tshsl-ns = <60>; >> + cdns,tsd2d-ns = <60>; >> + cdns,tchsh-ns = <60>; >> + cdns,tslch-ns = <60>; >> + cdns,read-delay = <2>; >> + #address-cells = <1>; >> + #size-cells = <1>; > > Are you sure these are correct? Aren't they marked as deprecated? Right. I found that "address-cells" and "size-cells" are deprecated. I will remove these in the next series. Thank you for reviewing the patch. > > > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index fa38940fe6cd..76b420379645 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -206,6 +206,20 @@ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; &main_gpio2 { @@ -347,6 +361,31 @@ maximum-speed = "high-speed"; }; +&fss { + status = "okay"; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..9fe255f0576e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -79,3 +101,24 @@ pinctrl-names = "default"; phys = <&transceiver0>; }; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +};