| Message ID | 1677490575-29092-1-git-send-email-quic_krichai@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 8a63441e83724fee1ef3fd37b237d40d90780766 |
| Headers | show |
| Series | [V1] arm64:dts:qcom:sc7280: mark memory of PCIe as cache coherent | expand |
Please fix the subject as: arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent On Mon, Feb 27, 2023 at 03:06:15PM +0530, Krishna chaitanya chundru wrote: > Mark the PCIe node as dma-coherent as the devices on PCIe bus are > cache coherent. > But this is a bug fix actually. If the controller is not marked as cache coherent, then kernel will try to ensure coherency during dma-ops and that may cause data corruption. So please add fixes tag and CC stable. Thanks, Mani > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index bdcb749..8f4ab6b 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2131,6 +2131,8 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pcie1_clkreq_n>; > > + dma-coherent; > + > iommus = <&apps_smmu 0x1c80 0x1>; > > iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, > -- > 2.7.4 >
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bdcb749..8f4ab6b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2131,6 +2131,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; + dma-coherent; + iommus = <&apps_smmu 0x1c80 0x1>; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
Mark the PCIe node as dma-coherent as the devices on PCIe bus are cache coherent. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+)