Message ID | 20230212123805.30799-1-shentey@gmail.com (mailing list archive) |
---|---|
Headers | show |
Series | Consolidate PIIX south bridges | expand |
Am 12. Februar 2023 12:37:42 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >This series consolidates the implementations of the PIIX3 and PIIX4 south > >bridges and is an extended version of [1]. The motivation is to share as much > >code as possible and to bring both device models to feature parity such that > >perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This > >could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this > >list before. > > > >The series is structured as follows: > > > >Move sub devices into the PIIX3 south bridge, like PIIX4 does already: > >* hw/i386/pc: Create RTC controllers in south bridges > >* hw/i386/pc: No need for rtc_state to be an out-parameter > >* hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge > >* hw/isa/piix3: Create USB controller in host device > >* hw/isa/piix3: Create power management controller in host device > >* hw/isa/piix3: Move ISA bus IRQ assignments into host device > >* hw/isa/piix3: Create IDE controller in host device > >* hw/isa/piix3: Wire up ACPI interrupt internally > > > >Make PIIX3 and PIIX4 south bridges more similar: > >* hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS > >* hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 > >* hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 > >* hw/isa/piix3: Drop the "3" from PIIX base class > >* hw/isa/piix4: Make PIIX4's ACPI and USB functions optional > >* hw/isa/piix4: Remove unused inbound ISA interrupt lines > >* hw/isa/piix4: Reuse struct PIIXState from PIIX3 > >* hw/isa/piix4: Create the "intr" property during init() already > >* hw/isa/piix4: Rename reset control operations to match PIIX3 > > > >This patch achieves the main goal of the series: > >* hw/isa/piix3: Merge hw/isa/piix4.c > > > >Perform some further consolidations which were easier to do after the merge: > >* hw/isa/piix: Harmonize names of reset control memory regions > >* hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 > >* hw/isa/piix: Rename functions to be shared for interrupt triggering > >* hw/isa/piix: Consolidate IRQ triggering > >* hw/isa/piix: Share PIIX3's base class with PIIX4 > > > >One challenge was dealing with optional devices where Peter already gave advice > >in [1] which this series implements. > > > >There are still some differences in the device models: > >- PIIX4 instantiates its own PIC and PIT while PIIX3 doesn't > >- PIIX4 wires up the RTC IRQ itself while PIIX3 doesn't > >- Different binary layout in VM state > > > >v7: > >- Rebase onto master > >- Avoid the PIC proxy (Phil) > > The motivation for the PIC proxy was to allow for wiring up ISA interrupts in > > the south bridges. ISA interrupt wiring requires the GPIO lines to be > > populated already but pc_piix assigned the interrupts only after realizing > > PIIX3. By shifting interrupt assignment before realizing, the ISA interrupts > > are already populated during PIIX3's realize phase where the ISA interrupts > > are wired up. > >- New patches: > > * hw/isa/piix4: Reuse struct PIIXState from PIIX3 > > * hw/isa/piix4: Create the "intr" property during init() already > >- Patches with substantial changes (Reviewed-by dropped): > > * hw/isa/piix3: Move ISA bus IRQ assignments into host device > Ping Can we queue the piix3 part already? Now that the series doesn't introduce a PIC proxy any more the piix3 part is essentially QOM cleanup. Note that I cautiously dropped some Reviewed-by tags in the piix3 part as well. Best regards, Bernhard > > >Testing done: > >* `make check` > >* Boot live CD: > > * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` > > * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` > >* 'qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=ttyS0"` > >* Run HVM domU guest under Xen with manjaro-kde-21.3.2-220704-linux515.iso image > > > >v6: > >- Fix some comments about TYPE_ISA_PIC (Mark) ... and use it consistently > > within the patch series. > >- Incorporate series "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south > > bridges" [2] for maintainer convenience. > >- Merge v5's 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is > > created' into > > https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03312.html . Do > > similar for Malta. > >- Rebase onto latest master (d6271b657286 "Merge tag 'for_upstream' of > > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging") > > > >v5: > >- Pick up Reviewed-by tags from https://lists.nongnu.org/archive/html/qemu-devel/2023-01/msg00116.html > >- Add patch to make usage of the isa_pic global more type-safe > >- Re-introduce isa-pic as PIC specific proxy (Mark) > > > >v4: > >- Rebase onto "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" > > since it is already queued via mips-next. This eliminates patches > > 'hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"' and 'hw/isa/piix4: > > Prefix pci_slot_get_pirq() with "piix4_"'. > >- Squash 'hw/isa/piix: Drop the "3" from the PIIX base class' into > > 'hw/isa/piix3: Rename typedef PIIX3State to PIIXState'. I originally only > > split these patches since I wasn't sure whether renaming a type was allowed. > >- Add new patch 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is > > created' for forther cleanup of INTx-to-LNKx route decoupling. > > > >v3: > >- Introduce one TYPE_ICH9_USB_UHCI(fn) rather than several TYPE_ICH9_USB_UHCIx > > (Philippe) > >- Make proxy PIC generic (Philippe) > >- Track Malta's PIIX dependencies through KConfig > >- Rebase onto Philippe's 'hw/isa/piix4: Remove MIPS Malta specific bits' series [3] > >- Also rebase onto latest master to resolve merge conflicts. This required > > copying Philippe's series as first three patches - please ignore. > > > >v2: > >- Introduce TYPE_ defines for IDE and USB device models (Mark) > >- Omit unexporting of PIIXState (Mark) > >- Improve commit message of patch 5 to mention reset triggering through PCI > > configuration space (Mark) > >- Move reviewed patches w/o dependencies to the bottom of the series for early > > upstreaming > > > >[1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html > >[2] https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03310.html > >[3] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg05367.html > > > >Bernhard Beschow (23): > > hw/i386/pc: Create RTC controllers in south bridges > > hw/i386/pc: No need for rtc_state to be an out-parameter > > hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 > > south bridge > > hw/isa/piix3: Create USB controller in host device > > hw/isa/piix3: Create power management controller in host device > > hw/isa/piix3: Move ISA bus IRQ assignments into host device > > hw/isa/piix3: Create IDE controller in host device > > hw/isa/piix3: Wire up ACPI interrupt internally > > hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS > > hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 > > hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 > > hw/isa/piix3: Drop the "3" from PIIX base class > > hw/isa/piix4: Make PIIX4's ACPI and USB functions optional > > hw/isa/piix4: Remove unused inbound ISA interrupt lines > > hw/isa/piix4: Reuse struct PIIXState from PIIX3 > > hw/isa/piix4: Create the "intr" property during init() already > > hw/isa/piix4: Rename reset control operations to match PIIX3 > > hw/isa/piix3: Merge hw/isa/piix4.c > > hw/isa/piix: Harmonize names of reset control memory regions > > hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 > > hw/isa/piix: Rename functions to be shared for interrupt triggering > > hw/isa/piix: Consolidate IRQ triggering > > hw/isa/piix: Share PIIX3's base class with PIIX4 > > > > MAINTAINERS | 6 +- > > include/hw/i386/ich9.h | 2 + > > include/hw/i386/pc.h | 2 +- > > include/hw/southbridge/piix.h | 28 +++- > > hw/i386/pc.c | 16 +- > > hw/i386/pc_piix.c | 67 ++++---- > > hw/i386/pc_q35.c | 3 +- > > hw/isa/lpc_ich9.c | 8 + > > hw/isa/{piix3.c => piix.c} | 306 ++++++++++++++++++++++++++-------- > > hw/isa/piix4.c | 302 --------------------------------- > > hw/mips/malta.c | 6 +- > > hw/i386/Kconfig | 3 +- > > hw/isa/Kconfig | 8 +- > > hw/isa/meson.build | 3 +- > > hw/mips/Kconfig | 2 +- > > 15 files changed, 333 insertions(+), 429 deletions(-) > > rename hw/isa/{piix3.c => piix.c} (55%) > > delete mode 100644 hw/isa/piix4.c > > > >-- > >2.39.1 > > >
On Thu, Feb 23, 2023 at 05:25:23PM +0000, Bernhard Beschow wrote: > Ping > > Can we queue the piix3 part already? Now that the series doesn't introduce a PIC proxy any more the piix3 part is essentially QOM cleanup. > > Note that I cautiously dropped some Reviewed-by tags in the piix3 part as well. > > Best regards, > Bernhard This conflicts with ICH9 cleanup - I guess once that is merged you will rebase right?
Am 1. März 2023 22:19:12 UTC schrieb "Michael S. Tsirkin" <mst@redhat.com>: >On Thu, Feb 23, 2023 at 05:25:23PM +0000, Bernhard Beschow wrote: >> Ping >> >> Can we queue the piix3 part already? Now that the series doesn't introduce a PIC proxy any more the piix3 part is essentially QOM cleanup. >> >> Note that I cautiously dropped some Reviewed-by tags in the piix3 part as well. >> >> Best regards, >> Bernhard > >This conflicts with ICH9 cleanup - I guess once that is merged you will >rebase right? I did -- v8 is out! Best regards, Bernhard