| Message ID | 20230301091136.17862-4-r-gunasekaran@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: j721s2: Add support for additional IPs | expand |
On 3/1/23 3:11 AM, Ravi Gunasekaran wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > Add support for two instance of OSPI in J721S2 SoC. > > Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > Changes from v11: > * Cleaned up comments > > Changes from v10: > * Documented the reason for disabling the nodes by default. > * Removed Link tag from commmit message > > Changes from v9: > * Disabled fss, ospi nodes by default in common DT file > > Changes from v8: > * Updated "ranges" property to fix dtbs warnings > > Changes from v7: > * Removed "reg" property from syscon node > * Renamed the "syscon" node to "bus" to after change in > compatible property > > Changes from v6: > * Fixed the syscon node's compatible property > > Changes from v5: > * Updated the syscon node's compatible property > * Removed Cc tags from commit message > > Changes from v4: > * No change > > Changes from v3: > * No change > > Changes from v2: > * No change > > Changes from v1: > * No change > > .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > index 0af242aa9816..ab3ce8be7216 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > @@ -306,4 +306,50 @@ > ti,cpts-periodic-outputs = <2>; > }; > }; > + > + fss: bus@47000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, > + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, > + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; > + > + status = "disabled"; Since this node doesn't need pinmux, why is it default disabled? Same for the other parent nodes in this series. Andrew > + > + ospi0: spi@47040000 { > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > + reg = <0x00 0x47040000 0x00 0x100>, > + <0x05 0x00000000 0x01 0x00000000>; > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 109 5>; > + assigned-clocks = <&k3_clks 109 5>; > + assigned-clock-parents = <&k3_clks 109 7>; > + assigned-clock-rates = <166666666>; > + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; /* Needs pinmux */ > + }; > + > + ospi1: spi@47050000 { > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > + reg = <0x00 0x47050000 0x00 0x100>, > + <0x07 0x00000000 0x01 0x00000000>; > + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 110 5>; > + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; /* Needs pinmux */ > + }; > + }; > };
On 01/03/23 9:27 pm, Andrew Davis wrote: > On 3/1/23 3:11 AM, Ravi Gunasekaran wrote: >> From: Aswath Govindraju <a-govindraju@ti.com> >> >> Add support for two instance of OSPI in J721S2 SoC. >> >> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> >> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> >> Signed-off-by: Matt Ranostay <mranostay@ti.com> >> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >> --- >> Changes from v11: >> * Cleaned up comments >> >> Changes from v10: >> * Documented the reason for disabling the nodes by default. >> * Removed Link tag from commmit message >> >> Changes from v9: >> * Disabled fss, ospi nodes by default in common DT file >> >> Changes from v8: >> * Updated "ranges" property to fix dtbs warnings >> >> Changes from v7: >> * Removed "reg" property from syscon node >> * Renamed the "syscon" node to "bus" to after change in >> compatible property >> >> Changes from v6: >> * Fixed the syscon node's compatible property >> >> Changes from v5: >> * Updated the syscon node's compatible property >> * Removed Cc tags from commit message >> >> Changes from v4: >> * No change >> >> Changes from v3: >> * No change >> >> Changes from v2: >> * No change >> >> Changes from v1: >> * No change >> >> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 46 +++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi >> index 0af242aa9816..ab3ce8be7216 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi >> @@ -306,4 +306,50 @@ >> ti,cpts-periodic-outputs = <2>; >> }; >> }; >> + >> + fss: bus@47000000 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, >> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, >> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; >> + >> + status = "disabled"; > > Since this node doesn't need pinmux, why is it default disabled? Same for > the other parent nodes in this series. > > Andrew In this patch and others in this series, since child node is disabled, I thought of disabling the parent as well. And to later enable the parent node at the time when the child node needs to be enabled. > >> + >> + ospi0: spi@47040000 { >> + compatible = "ti,am654-ospi", "cdns,qspi-nor"; >> + reg = <0x00 0x47040000 0x00 0x100>, >> + <0x05 0x00000000 0x01 0x00000000>; >> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; >> + cdns,fifo-depth = <256>; >> + cdns,fifo-width = <4>; >> + cdns,trigger-address = <0x0>; >> + clocks = <&k3_clks 109 5>; >> + assigned-clocks = <&k3_clks 109 5>; >> + assigned-clock-parents = <&k3_clks 109 7>; >> + assigned-clock-rates = <166666666>; >> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; /* Needs pinmux */ >> + }; >> + >> + ospi1: spi@47050000 { >> + compatible = "ti,am654-ospi", "cdns,qspi-nor"; >> + reg = <0x00 0x47050000 0x00 0x100>, >> + <0x07 0x00000000 0x01 0x00000000>; >> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; >> + cdns,fifo-depth = <256>; >> + cdns,fifo-width = <4>; >> + cdns,trigger-address = <0x0>; >> + clocks = <&k3_clks 110 5>; >> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; /* Needs pinmux */ >> + }; >> + }; >> };
Andrew, On 02/03/23 9:03 am, Ravi Gunasekaran wrote: > > > On 01/03/23 9:27 pm, Andrew Davis wrote: >> On 3/1/23 3:11 AM, Ravi Gunasekaran wrote: >>> From: Aswath Govindraju <a-govindraju@ti.com> >>> >>> Add support for two instance of OSPI in J721S2 SoC. >>> >>> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> >>> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> >>> Signed-off-by: Matt Ranostay <mranostay@ti.com> >>> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >>> --- [...] >>> >>> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 46 +++++++++++++++++++ >>> 1 file changed, 46 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi >>> index 0af242aa9816..ab3ce8be7216 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi >>> @@ -306,4 +306,50 @@ >>> ti,cpts-periodic-outputs = <2>; >>> }; >>> }; >>> + >>> + fss: bus@47000000 { >>> + compatible = "simple-bus"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, >>> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, >>> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; >>> + >>> + status = "disabled"; >> >> Since this node doesn't need pinmux, why is it default disabled? Same for >> the other parent nodes in this series. >> >> Andrew > > In this patch and others in this series, since child node is disabled, > I thought of disabling the parent as well. And to later enable the > parent node at the time when the child node needs to be enabled. > Could you please provide your input on this? If the preferred way is to keep the parent node enabled, then I will do so. For the IPs added in this series, if the parent node needs additional information such as pinmux, gpio, I will disable both parent and child. And if only child node(s) need additional info, then I will keep the parent enabled and children disabled. >> >>> + >>> + ospi0: spi@47040000 { >>> + compatible = "ti,am654-ospi", "cdns,qspi-nor"; >>> + reg = <0x00 0x47040000 0x00 0x100>, >>> + <0x05 0x00000000 0x01 0x00000000>; >>> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; >>> + cdns,fifo-depth = <256>; >>> + cdns,fifo-width = <4>; >>> + cdns,trigger-address = <0x0>; >>> + clocks = <&k3_clks 109 5>; >>> + assigned-clocks = <&k3_clks 109 5>; >>> + assigned-clock-parents = <&k3_clks 109 7>; >>> + assigned-clock-rates = <166666666>; >>> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + status = "disabled"; /* Needs pinmux */ >>> + }; >>> + >>> + ospi1: spi@47050000 { >>> + compatible = "ti,am654-ospi", "cdns,qspi-nor"; >>> + reg = <0x00 0x47050000 0x00 0x100>, >>> + <0x07 0x00000000 0x01 0x00000000>; >>> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; >>> + cdns,fifo-depth = <256>; >>> + cdns,fifo-width = <4>; >>> + cdns,trigger-address = <0x0>; >>> + clocks = <&k3_clks 110 5>; >>> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + status = "disabled"; /* Needs pinmux */ >>> + }; >>> + }; >>> }; >
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..ab3ce8be7216 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,50 @@ ti,cpts-periodic-outputs = <2>; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + status = "disabled"; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + }; };