| Message ID | 138da2735f92c8b6f8578ec2e5a794ee515b665f.1677937317.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [net] net: ethernet: mtk_eth_soc: fix RX data corruption issue | expand |
On Sat, Mar 04, 2023 at 01:43:20PM +0000, Daniel Golle wrote: > Fix data corruption issue with SerDes connected PHYs operating at 1.25 > Gbps speed where we could previously observe about 30% packet loss while > the bad packet counter was increasing. > > As almost all boards with MediaTek MT7622 or MT7986 use either the MT7531 > switch IC operating at 3.125Gbps SerDes rate or single-port PHYs using > rate-adaptation to 2500Base-X mode, this issue only got exposed now when > we started trying to use SFP modules operating with 1.25 Gbps with the > BananaPi R3 board. > > The fix is to set bit 12 which disables the RX FIFO clear function when > setting up MAC MCR, MediaTek SDK did the same change stating: > "If without this patch, kernel might receive invalid packets that are > corrupted by GMAC."[1] > > [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/d8a2975939a12686c4a95c40db21efdc3f821f63 > > Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC") > Tested-by: Bjørn Mork <bjorn@mork.no> > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- I don't see something particularly controversial with this change. Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
On 3/4/23 05:43, Daniel Golle wrote: > Fix data corruption issue with SerDes connected PHYs operating at 1.25 > Gbps speed where we could previously observe about 30% packet loss while > the bad packet counter was increasing. > > As almost all boards with MediaTek MT7622 or MT7986 use either the MT7531 > switch IC operating at 3.125Gbps SerDes rate or single-port PHYs using > rate-adaptation to 2500Base-X mode, this issue only got exposed now when > we started trying to use SFP modules operating with 1.25 Gbps with the > BananaPi R3 board. > > The fix is to set bit 12 which disables the RX FIFO clear function when > setting up MAC MCR, MediaTek SDK did the same change stating: > "If without this patch, kernel might receive invalid packets that are > corrupted by GMAC."[1] > > [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/d8a2975939a12686c4a95c40db21efdc3f821f63 > > Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC") > Tested-by: Bjørn Mork <bjorn@mork.no> > Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Hello: This patch was applied to netdev/net.git (main) by Jakub Kicinski <kuba@kernel.org>: On Sat, 4 Mar 2023 13:43:20 +0000 you wrote: > Fix data corruption issue with SerDes connected PHYs operating at 1.25 > Gbps speed where we could previously observe about 30% packet loss while > the bad packet counter was increasing. > > As almost all boards with MediaTek MT7622 or MT7986 use either the MT7531 > switch IC operating at 3.125Gbps SerDes rate or single-port PHYs using > rate-adaptation to 2500Base-X mode, this issue only got exposed now when > we started trying to use SFP modules operating with 1.25 Gbps with the > BananaPi R3 board. > > [...] Here is the summary with links: - [net] net: ethernet: mtk_eth_soc: fix RX data corruption issue https://git.kernel.org/netdev/net/c/193250ace270 You are awesome, thank you!
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 14be6ea51b88..3cb43623d3db 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -616,7 +616,8 @@ static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); mcr_new = mcr_cur; mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | - MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; + MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | + MAC_MCR_RX_FIFO_CLR_DIS; /* Only update control register when needed! */ if (mcr_new != mcr_cur) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index afc9d52e79bf..b65de174c3d9 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -397,6 +397,7 @@ #define MAC_MCR_FORCE_MODE BIT(15) #define MAC_MCR_TX_EN BIT(14) #define MAC_MCR_RX_EN BIT(13) +#define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) #define MAC_MCR_BACKOFF_EN BIT(9) #define MAC_MCR_BACKPR_EN BIT(8) #define MAC_MCR_FORCE_RX_FC BIT(5)
Fix data corruption issue with SerDes connected PHYs operating at 1.25 Gbps speed where we could previously observe about 30% packet loss while the bad packet counter was increasing. As almost all boards with MediaTek MT7622 or MT7986 use either the MT7531 switch IC operating at 3.125Gbps SerDes rate or single-port PHYs using rate-adaptation to 2500Base-X mode, this issue only got exposed now when we started trying to use SFP modules operating with 1.25 Gbps with the BananaPi R3 board. The fix is to set bit 12 which disables the RX FIFO clear function when setting up MAC MCR, MediaTek SDK did the same change stating: "If without this patch, kernel might receive invalid packets that are corrupted by GMAC."[1] [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/d8a2975939a12686c4a95c40db21efdc3f821f63 Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC") Tested-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 ++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) base-commit: 528125268588a18a2f257002af051b62b14bb282