| Message ID | 1678080302-29691-7-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PCIe EP support for SDX65 | expand |
On 6.03.2023 06:25, Rohit Agarwal wrote: > Enable PCIe Endpoint controller on the SDX65 MTP board based > on Qualcomm SDX65 platform. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > index 86bb853..952de105 100644 > --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts > +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts > @@ -252,6 +252,14 @@ > vdda-pll-supply = <&vreg_l4b_0p88>; > }; > > +&pcie_ep { > + status = "okay"; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default > + &pcie_ep_wake_default>; status last pinctrl-n goes before pinctrl-names > +}; > + > &qpic_bam { > status = "okay"; > }; > @@ -276,6 +284,44 @@ > memory-region = <&mpss_adsp_mem>; > }; > > ++&tlmm { > + pcie_ep_clkreq_default: pcie_ep_clkreq_default { No underscores in node names, pinctrl children node names must end in -state. Please check your patches against "make dtbs_check" > + mux { > + pins = "gpio56"; > + function = "pcie_clkreq"; > + }; > + config { > + pins = "gpio56"; > + drive-strength = <2>; > + bias-disable; > + }; mux {} / config {} is unnecessary. You can simply do: { pins = "gpio56"; function = "pcie_clkreq"; drive-strength = <2>; bias-disable; }; Konrad > + }; > + > + pcie_ep_perst_default: pcie_ep_perst_default { > + mux { > + pins = "gpio57"; > + function = "gpio"; > + }; > + config { > + pins = "gpio57"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + }; > + > + pcie_ep_wake_default: pcie_ep_wake_default { > + mux { > + pins = "gpio53"; > + function = "gpio"; > + }; > + config { > + pins = "gpio53"; > + drive-strength = <2>; > + bias-disable; > + }; > + }; > +}; > + > &usb { > status = "okay"; > };
On 3/6/2023 4:02 PM, Konrad Dybcio wrote: > > On 6.03.2023 06:25, Rohit Agarwal wrote: >> Enable PCIe Endpoint controller on the SDX65 MTP board based >> on Qualcomm SDX65 platform. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts >> index 86bb853..952de105 100644 >> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts >> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts >> @@ -252,6 +252,14 @@ >> vdda-pll-supply = <&vreg_l4b_0p88>; >> }; >> >> +&pcie_ep { >> + status = "okay"; >> + >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default >> + &pcie_ep_wake_default>; > status last > > pinctrl-n goes before pinctrl-names >> +}; >> + >> &qpic_bam { >> status = "okay"; >> }; >> @@ -276,6 +284,44 @@ >> memory-region = <&mpss_adsp_mem>; >> }; >> >> ++&tlmm { >> + pcie_ep_clkreq_default: pcie_ep_clkreq_default { > No underscores in node names, pinctrl children node names > must end in -state. Please check your patches against > "make dtbs_check" >> + mux { >> + pins = "gpio56"; >> + function = "pcie_clkreq"; >> + }; >> + config { >> + pins = "gpio56"; >> + drive-strength = <2>; >> + bias-disable; >> + }; > mux {} / config {} is unnecessary. You can simply do: > > { > pins = "gpio56"; > function = "pcie_clkreq"; > drive-strength = <2>; > bias-disable; > }; Thanks for detailed explanation. Will rectify all in the next version. Thanks, Rohit. > Konrad >> + }; >> + >> + pcie_ep_perst_default: pcie_ep_perst_default { >> + mux { >> + pins = "gpio57"; >> + function = "gpio"; >> + }; >> + config { >> + pins = "gpio57"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> + }; >> + >> + pcie_ep_wake_default: pcie_ep_wake_default { >> + mux { >> + pins = "gpio53"; >> + function = "gpio"; >> + }; >> + config { >> + pins = "gpio53"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + }; >> +}; >> + >> &usb { >> status = "okay"; >> };
Hi Rohit,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on lee-mfd/for-mfd-next lee-mfd/for-mfd-fixes pci/next pci/for-linus linus/master v6.3-rc1 next-20230306]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Rohit-Agarwal/dt-bindings-mfd-qcom-tcsr-Add-compatible-for-sdx65/20230306-132618
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/1678080302-29691-7-git-send-email-quic_rohiagar%40quicinc.com
patch subject: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230307/202303071612.HZ9bDCp7-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/51b8272710554bf9cbee6604f73951179e85ffa7
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Rohit-Agarwal/dt-bindings-mfd-qcom-tcsr-Add-compatible-for-sdx65/20230306-132618
git checkout 51b8272710554bf9cbee6604f73951179e85ffa7
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303071612.HZ9bDCp7-lkp@intel.com/
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/qcom-sdx65-mtp.dts:287.1-2 syntax error
FATAL ERROR: Unable to parse input tree
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 86bb853..952de105 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -252,6 +252,14 @@ vdda-pll-supply = <&vreg_l4b_0p88>; }; +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "okay"; }; @@ -276,6 +284,44 @@ memory-region = <&mpss_adsp_mem>; }; ++&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb { status = "okay"; };
Enable PCIe Endpoint controller on the SDX65 MTP board based on Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)