diff mbox series

[v14,6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold

Message ID 20230209105628.50294-7-bchihi@baylibre.com (mailing list archive)
State New, archived
Delegated to: Daniel Lezcano
Headers show
Series Add LVTS Thermal Architecture | expand

Commit Message

Balsam CHIHI Feb. 9, 2023, 10:56 a.m. UTC 
From: Balsam CHIHI <bchihi@baylibre.com>

The mt8195 SoC has several hotspots around the CPUs. Specify the
targeted temperature threshold when to apply the mitigation and define
the associated cooling devices.

Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 169 ++++++++++++++++++++---
 1 file changed, 153 insertions(+), 16 deletions(-)

Comments

Balsam CHIHI Feb. 14, 2023, 2:43 p.m. UTC | #1 
Hi Matthias, Angelo,

Would you please confirm if this patch can be applied?
and, if it is the case, to which tree it will be applied?

Best regards,
Balsam
AngeloGioacchino Del Regno Feb. 15, 2023, 12:50 p.m. UTC | #2 
Il 14/02/23 15:43, Balsam CHIHI ha scritto:
> Hi Matthias, Angelo,
> 
> Would you please confirm if this patch can be applied?
> and, if it is the case, to which tree it will be applied?
> 
> Best regards,
> Balsam

I think it's fine to apply 5/6 and 6/6, as you're adding pre-Tjunction
max temperature - this is not board specific, but rather SoC-specific.
In reality it's practically the same for most SoCs, even.

Each board will define extensions (that are thermal envelope dependant)
to these "please-dont-burn-my-device" initial thresholds, but that's a
story for another day, and for other people anyway (including me).

Matthias, over to you!
Balsam CHIHI Feb. 15, 2023, 1:13 p.m. UTC | #3 
Hi Angelo,

On Wed, Feb 15, 2023 at 1:50 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 14/02/23 15:43, Balsam CHIHI ha scritto:
> > Hi Matthias, Angelo,
> >
> > Would you please confirm if this patch can be applied?
> > and, if it is the case, to which tree it will be applied?
> >
> > Best regards,
> > Balsam
>
> I think it's fine to apply 5/6 and 6/6, as you're adding pre-Tjunction
> max temperature - this is not board specific, but rather SoC-specific.
> In reality it's practically the same for most SoCs, even.
>
> Each board will define extensions (that are thermal envelope dependant)
> to these "please-dont-burn-my-device" initial thresholds, but that's a
> story for another day, and for other people anyway (including me).
>
> Matthias, over to you!

Indeed.
Thank you for your feedback!

Best regards,
Balsam
Balsam CHIHI March 7, 2023, 11:10 a.m. UTC | #4 
Hi Matthias,

Is it time to apply those last two patches of the series "Add LVTS
Thermal Architecture"?

[v14,6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold
https://lore.kernel.org/all/20230209105628.50294-7-bchihi@baylibre.com/
and
[v14,5/6] arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes
https://lore.kernel.org/all/20230209105628.50294-6-bchihi@baylibre.com/

Is there anything that I could do from my side, to make it possible?

Best regards,
Balsam
Matthias Brugger March 31, 2023, 10:36 a.m. UTC | #5 
On 07/03/2023 12:10, Balsam CHIHI wrote:
> Hi Matthias,
> 
> Is it time to apply those last two patches of the series "Add LVTS
> Thermal Architecture"?
> 
> [v14,6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold
> https://lore.kernel.org/all/20230209105628.50294-7-bchihi@baylibre.com/
> and
> [v14,5/6] arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes
> https://lore.kernel.org/all/20230209105628.50294-6-bchihi@baylibre.com/
> 
> Is there anything that I could do from my side, to make it possible?
> 

Both applied now. Thanks!
Balsam CHIHI March 31, 2023, 11:11 a.m. UTC | #6 
Hi Matthias,

On Fri, Mar 31, 2023 at 12:36 PM Matthias Brugger
<matthias.bgg@gmail.com> wrote:
>
>
>
> On 07/03/2023 12:10, Balsam CHIHI wrote:
> > Hi Matthias,
> >
> > Is it time to apply those last two patches of the series "Add LVTS
> > Thermal Architecture"?
> >
> > [v14,6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold
> > https://lore.kernel.org/all/20230209105628.50294-7-bchihi@baylibre.com/
> > and
> > [v14,5/6] arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes
> > https://lore.kernel.org/all/20230209105628.50294-6-bchihi@baylibre.com/
> >
> > Is there anything that I could do from my side, to make it possible?
> >
>
> Both applied now. Thanks!

Great, Thank you!

Best Regards,
Balsam
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c7e958f8f1b5a..10c8fb0856bc4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -14,6 +14,7 @@ 
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
 #include <dt-bindings/power/mt8195-power.h>
 #include <dt-bindings/reset/mt8195-resets.h>
+#include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
 
 / {
@@ -2413,107 +2414,243 @@  dp_tx: dp-tx@1c600000 {
 
 	thermal_zones: thermal-zones {
 		cpu0-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
+
 			trips {
+				cpu0_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu0_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu1-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
+
 			trips {
+				cpu1_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu1_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu2-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
+
 			trips {
+				cpu2_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu2_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu3-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
+
 			trips {
+				cpu3_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu3_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu4-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
+
 			trips {
+				cpu4_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu4_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu4_alert>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu5-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
+
 			trips {
+				cpu5_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu5_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu5_alert>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu6-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
+
 			trips {
+				cpu6_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu6_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu6_alert>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu7-thermal {
-			polling-delay = <0>;
-			polling-delay-passive = <0>;
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
 			thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
+
 			trips {
+				cpu7_alert: trip-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
 				cpu7_crit: trip-crit {
 					temperature = <100000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu7_alert>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 	};
 };