| Message ID | 20230106010155.26868-2-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: sunxi: Add MangoPi MQ-R board support | expand |
On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote: > The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical > die as their R528/T113-s siblings with ARM Cortex-A7 cores. > > To allow sharing the basic SoC .dtsi files across those two > architectures as well, introduce a symlink to the RISC-V DT directory. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > scripts/dtc/include-prefixes/riscv | 1 + > 1 file changed, 1 insertion(+) > create mode 120000 scripts/dtc/include-prefixes/riscv > > diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv > new file mode 120000 > index 0000000000000..2025094189380 > --- /dev/null > +++ b/scripts/dtc/include-prefixes/riscv > @@ -0,0 +1 @@ > +../../../arch/riscv/boot/dts > \ No newline at end of file > -- > 2.35.5 > >
On Thu, 05 Jan 2023 17:01:52 PST (-0800), andre.przywara@arm.com wrote: > The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical > die as their R528/T113-s siblings with ARM Cortex-A7 cores. > > To allow sharing the basic SoC .dtsi files across those two > architectures as well, introduce a symlink to the RISC-V DT directory. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > scripts/dtc/include-prefixes/riscv | 1 + > 1 file changed, 1 insertion(+) > create mode 120000 scripts/dtc/include-prefixes/riscv > > diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv > new file mode 120000 > index 0000000000000..2025094189380 > --- /dev/null > +++ b/scripts/dtc/include-prefixes/riscv > @@ -0,0 +1 @@ > +../../../arch/riscv/boot/dts > \ No newline at end of file Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv new file mode 120000 index 0000000000000..2025094189380 --- /dev/null +++ b/scripts/dtc/include-prefixes/riscv @@ -0,0 +1 @@ +../../../arch/riscv/boot/dts \ No newline at end of file
The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- scripts/dtc/include-prefixes/riscv | 1 + 1 file changed, 1 insertion(+) create mode 120000 scripts/dtc/include-prefixes/riscv