| Message ID | 20230308104009.260451-7-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs | expand |
On 8.03.2023 11:40, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Enable the SPI interface exposed on the sa8775p-ride development board. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index 5fdce8279537..d01ca3a9ee37 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -14,6 +14,7 @@ / { > aliases { > serial0 = &uart10; > i2c18 = &i2c18; > + spi16 = &spi16; > }; > > chosen { > @@ -40,12 +41,25 @@ &sleep_clk { > clock-frequency = <32764>; > }; > > +&spi16 { > + pinctrl-0 = <&qup_spi16_default>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > &tlmm { > qup_uart10_default: qup-uart10-state { > pins = "gpio46", "gpio47"; > function = "qup1_se3"; > }; > > + qup_spi16_default: qup-spi16-state { > + pins = "gpio86", "gpio87", "gpio88", "gpio89"; Rather weird to have an identical configuration for all MOSI/MISO/CS/CLK pins.. Please doublecheck Konrad > + function = "qup2_se2"; > + drive-strength = <6>; > + bias-disable; > + }; > + > qup_i2c18_default: qup-i2c18-state { > pins = "gpio95", "gpio96"; > function = "qup2_se4";
On Wed, 8 Mar 2023 at 11:58, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 8.03.2023 11:40, Bartosz Golaszewski wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > > > Enable the SPI interface exposed on the sa8775p-ride development board. > > > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > > index 5fdce8279537..d01ca3a9ee37 100644 > > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > > @@ -14,6 +14,7 @@ / { > > aliases { > > serial0 = &uart10; > > i2c18 = &i2c18; > > + spi16 = &spi16; > > }; > > > > chosen { > > @@ -40,12 +41,25 @@ &sleep_clk { > > clock-frequency = <32764>; > > }; > > > > +&spi16 { > > + pinctrl-0 = <&qup_spi16_default>; > > + pinctrl-names = "default"; > > + status = "okay"; > > +}; > > + > > &tlmm { > > qup_uart10_default: qup-uart10-state { > > pins = "gpio46", "gpio47"; > > function = "qup1_se3"; > > }; > > > > + qup_spi16_default: qup-spi16-state { > > + pins = "gpio86", "gpio87", "gpio88", "gpio89"; > Rather weird to have an identical configuration for all > MOSI/MISO/CS/CLK pins.. Please doublecheck > This is in line with many other boards in arch/arm64/boot/dts/qcom/ that have the same config for all SPI pins. Some of them unnecessarily split the config into separate state nodes with the same config though. Bart > Konrad > > + function = "qup2_se2"; > > + drive-strength = <6>; > > + bias-disable; > > + }; > > + > > qup_i2c18_default: qup-i2c18-state { > > pins = "gpio95", "gpio96"; > > function = "qup2_se4";
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 5fdce8279537..d01ca3a9ee37 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -14,6 +14,7 @@ / { aliases { serial0 = &uart10; i2c18 = &i2c18; + spi16 = &spi16; }; chosen { @@ -40,12 +41,25 @@ &sleep_clk { clock-frequency = <32764>; }; +&spi16 { + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &tlmm { qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4";