| Message ID | 20230227090228.17117-1-ivan.klokov@syntacore.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix slli_uw decoding | expand |
On Mon, 27 Feb 2023 at 10:04, Ivan Klokov <ivan.klokov@syntacore.com> wrote: > > The decoding of the slli_uw currently contains decoding > error: shamt part of opcode has six bits, not five. > > Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
On Mon, Feb 27, 2023 at 7:06 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote: > > The decoding of the slli_uw currently contains decoding > error: shamt part of opcode has six bits, not five. > > Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > disas/riscv.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index ddda687c13..03cfefb0d3 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > + { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > @@ -2617,10 +2617,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) > switch (((inst >> 12) & 0b111)) { > case 0: op = rv_op_addiw; break; > case 1: > - switch (((inst >> 25) & 0b1111111)) { > + switch (((inst >> 26) & 0b111111)) { > case 0: op = rv_op_slliw; break; > - case 4: op = rv_op_slli_uw; break; > - case 48: > + case 2: op = rv_op_slli_uw; break; > + case 24: > switch ((inst >> 20) & 0b11111) { > case 0b00000: op = rv_op_clzw; break; > case 0b00001: op = rv_op_ctzw; break; > -- > 2.34.1 > >
On Mon, Feb 27, 2023 at 7:06 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote: > > The decoding of the slli_uw currently contains decoding > error: shamt part of opcode has six bits, not five. > > Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > disas/riscv.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index ddda687c13..03cfefb0d3 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > + { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > @@ -2617,10 +2617,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) > switch (((inst >> 12) & 0b111)) { > case 0: op = rv_op_addiw; break; > case 1: > - switch (((inst >> 25) & 0b1111111)) { > + switch (((inst >> 26) & 0b111111)) { > case 0: op = rv_op_slliw; break; > - case 4: op = rv_op_slli_uw; break; > - case 48: > + case 2: op = rv_op_slli_uw; break; > + case 24: > switch ((inst >> 20) & 0b11111) { > case 0b00000: op = rv_op_clzw; break; > case 0b00001: op = rv_op_ctzw; break; > -- > 2.34.1 > >
diff --git a/disas/riscv.c b/disas/riscv.c index ddda687c13..03cfefb0d3 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, @@ -2617,10 +2617,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) switch (((inst >> 12) & 0b111)) { case 0: op = rv_op_addiw; break; case 1: - switch (((inst >> 25) & 0b1111111)) { + switch (((inst >> 26) & 0b111111)) { case 0: op = rv_op_slliw; break; - case 4: op = rv_op_slli_uw; break; - case 48: + case 2: op = rv_op_slli_uw; break; + case 24: switch ((inst >> 20) & 0b11111) { case 0b00000: op = rv_op_clzw; break; case 0b00001: op = rv_op_ctzw; break;
The decoding of the slli_uw currently contains decoding error: shamt part of opcode has six bits, not five. Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> --- disas/riscv.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)