| Message ID | 20230312004445.15913-3-blarson@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support AMD Pensando Elba SoC | expand |
On 12/03/2023 01:44, Brad Larson wrote: > AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and > explicitly controls byte-lane enables. > > Signed-off-by: Brad Larson <blarson@amd.com> Thank you for your patch. There is something to discuss/improve. > interrupts: > maxItems: 1 > @@ -120,6 +119,27 @@ required: > - interrupts > - clocks > > +allOf: > + - $ref: mmc-controller.yaml > + - if: > + properties: > + compatible: > + contains: > + const: amd,pensando-elba-sd4hc > + then: > + properties: > + reg: > + items: > + - description: Host controller registers > + - description: Elba byte-lane enable register for writes > + required: > + - resets > + else: > + properties: > + resets: false I don't think this passed the tests... You disallow resets for everyone else. Why? Drop this line. > + reg: > + maxItems: 1 > + > unevaluatedProperties: false > > examples: Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index adacd0535c14..3c511c02e8a6 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -9,19 +9,18 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) maintainers: - Masahiro Yamada <yamada.masahiro@socionext.com> -allOf: - - $ref: mmc-controller.yaml - properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -120,6 +119,27 @@ required: - interrupts - clocks +allOf: + - $ref: mmc-controller.yaml + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-sd4hc + then: + properties: + reg: + items: + - description: Host controller registers + - description: Elba byte-lane enable register for writes + required: + - resets + else: + properties: + resets: false + reg: + maxItems: 1 + unevaluatedProperties: false examples:
AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson <blarson@amd.com> --- v11 changes: - Remove resets description and reset-names - Add descriptions for amd,pensando-elba-sd4hc reg items v10 changes: - Move reset-names property definition next to existing resets prop - Move allOf to the bottom and set resets/reset-names required only for pensando - Fix reg maxItems for existing, must be 1 v9 changes: - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-)