| Message ID | 20230314080443.64635-1-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | Qcom: LLCC/EDAC: Fix base address used for LLCC banks | expand |
On Tue, 14 Mar 2023 13:34:29 +0530, Manivannan Sadhasivam wrote: > The Qualcomm LLCC/EDAC drivers were using a fixed register stride for > accessing the (Control and Status Regsiters) CSRs of each LLCC bank. > This offset only works for some SoCs like SDM845 for which driver support > was initially added. > > But the later SoCs use different register stride that vary between the > banks with holes in-between. So it is not possible to use a single register > stride for accessing the CSRs of each bank. By doing so could result in a > crash with the current drivers. So far this crash is not reported since > EDAC_QCOM driver is not enabled in ARM64 defconfig and no one tested the > driver extensively by triggering the EDAC IRQ (that's where each bank > CSRs are accessed). > > [...] Applied, thanks! [03/14] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks commit: bfe088bde391824040c39cbf277d7fe782042936 [04/14] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks commit: 116a932bbc7bc740b068fbfe320a465811ca62f8 [05/14] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks commit: 62e5ee9db98ed67eb50205072135544055cba9c4 [06/14] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks commit: 0fe0955a79b994b8dcabe79f3a7192251fb256ea [07/14] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks commit: c5ccf8d33f11f57ef46d12db1dda4afcc4d5150b [08/14] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks commit: 42c9b1578233eeb3044656a446486bd2efc87312 [09/14] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks commit: 7ae317cba6be783cfd6155bceec91d0918f78fb8 [10/14] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks commit: 413c8ecd48f1df8034c7b13881ded33b3d10171f [11/14] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks commit: 65d9975e5dae4601e8902765d08f55c246fd2022 Best regards,
The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Regsiters) CSRs of each LLCC bank. This offset only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash with the current drivers. So far this crash is not reported since EDAC_QCOM driver is not enabled in ARM64 defconfig and no one tested the driver extensively by triggering the EDAC IRQ (that's where each bank CSRs are accessed). For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This series has been tested on SM8250, SM8450, SM6350, SC8280XP, SA8540P, and SDM845. Merging strategy ---------------- All patches should be merged to qcom tree due to LLCC dependency. Thanks, Mani Changes in v8: * Added the ECC polling support patch that was missed in v7 Changes in v7: * Rebased on top of v6.3-rc1 * Dropped the patches applied for v6.3 * Dropped Sai from the binding maintainers list since he left Qcom Changes in v6: * Incorporated comments from Borislav for the EDAC patches and collected review tags. Changes in v5: * Reduced the size of llcc0 to 0x45000 on SDM845 due to overlapping with BWMON * Added a patch to disable creation of EDAC platform device on SDM845 * Rebase on top of v6.2-rc1 * Moved the EDAC specific patches to the start so that they can be applied independently of LLCC patches Changes in v4: * Added a patch that fixes the use-after-free bug in qcom_edac driver Changes in v3: * Brought back reg-names property for compatibility (Krzysztof) * Removed Fixes tag and stable list as backporting the drivers/binding/dts patches alone would break (Krzysztof) * Fixed the uninitialized variable issue (Kbot) * Added a patch to make use of driver supplied polling interval (Luca) * Added a patch for module autoloading (Andrew) * Didn't collect Review tags from Sai as the dts patches were changed. Changes in v2: * Removed reg-names property and used index of reg property to parse LLCC bank base address (Bjorn) * Collected Ack from Sai for binding * Added a new patch for polling mode (Luca) * Renamed subject of patches targeting SC7180 and SM6350 Manivannan Sadhasivam (14): dt-bindings: arm: msm: Update the maintainers for LLCC dt-bindings: arm: msm: Fix register regions used for LLCC banks arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks qcom: llcc/edac: Fix the base address used for accessing LLCC banks qcom: llcc/edac: Support polling mode for ECC handling soc: qcom: llcc: Do not create EDAC platform device on SDM845 .../bindings/arm/msm/qcom,llcc.yaml | 128 ++++++++++++++++-- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +- drivers/edac/qcom_edac.c | 64 +++++---- drivers/soc/qcom/llcc-qcom.c | 87 +++++++----- include/linux/soc/qcom/llcc-qcom.h | 6 +- 13 files changed, 242 insertions(+), 97 deletions(-)