diff mbox series

[v5,12/21] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator

Message ID 20230311090733.56918-13-hal.feng@starfivetech.com (mailing list archive)
State Superseded, archived
Headers show
Series Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC | expand

Commit Message

Hal Feng March 11, 2023, 9:07 a.m. UTC 
From: Emil Renner Berthing <kernel@esmil.dk>

Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../clock/starfive,jh7110-aoncrg.yaml         | 107 ++++++++++++++++++
 .../dt-bindings/clock/starfive,jh7110-crg.h   |  18 +++
 .../dt-bindings/reset/starfive,jh7110-crg.h   |  12 ++
 3 files changed, 137 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml

Comments

Conor Dooley March 11, 2023, 1:14 p.m. UTC | #1 
On Sat, Mar 11, 2023 at 05:07:24PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add bindings for the always-on clock and reset generator (AONCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Always-On Clock and Reset Generator
> +
> +maintainers:
> +  - Emil Renner Berthing <kernel@esmil.dk>
> +
> +properties:
> +  compatible:
> +    const: starfive,jh7110-aoncrg
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    oneOf:
> +      - items:
> +          - description: Main Oscillator (24 MHz)
> +          - description: GMAC0 RMII reference or GMAC0 RGMII RX
> +          - description: STG AXI/AHB
> +          - description: APB Bus
> +          - description: GMAC0 GTX
> +
> +      - items:
> +          - description: Main Oscillator (24 MHz)
> +          - description: GMAC0 RMII reference or GMAC0 RGMII RX
> +          - description: STG AXI/AHB or GMAC0 RGMII RX
> +          - description: APB Bus or STG AXI/AHB
> +          - description: GMAC0 GTX or APB Bus
> +          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX

Something tells me that the use of "or" means we're not doing this
correctly.
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> +      - items:
> +          - description: Main Oscillator (24 MHz)
> +          - description: GMAC0 RMII reference
> +          - description: GMAC0 RGMII RX
> +          - description: STG AXI/AHB
> +          - description: APB Bus
> +          - description: GMAC0 GTX
> +          - description: RTC Oscillator (32.768 kHz)
> +
> +  clock-names:
> +    oneOf:
> +      - minItems: 5
> +        items:
> +          - const: osc
> +          - enum:
> +              - gmac0_rmii_refin
> +              - gmac0_rgmii_rxin
> +          - const: stg_axiahb
> +          - const: apb_bus
> +          - const: gmac0_gtxclk
> +          - const: rtc_osc
> +
> +      - minItems: 6
> +        items:
> +          - const: osc
> +          - const: gmac0_rmii_refin
> +          - const: gmac0_rgmii_rxin
> +          - const: stg_axiahb
> +          - const: apb_bus
> +          - const: gmac0_gtxclk
> +          - const: rtc_osc
Rob Herring (Arm) March 11, 2023, 2:18 p.m. UTC | #2 
On Sat, 11 Mar 2023 17:07:24 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add bindings for the always-on clock and reset generator (AONCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../clock/starfive,jh7110-aoncrg.yaml         | 107 ++++++++++++++++++
>  .../dt-bindings/clock/starfive,jh7110-crg.h   |  18 +++
>  .../dt-bindings/reset/starfive,jh7110-crg.h   |  12 ++
>  3 files changed, 137 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> 


Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.

If a tag was not added on purpose, please state why and what changed.

Missing tags:

Reviewed-by: Rob Herring <robh@kernel.org>
Hal Feng March 13, 2023, 2:49 a.m. UTC | #3 
On Sat, 11 Mar 2023 08:18:03 -0600, Rob Herring wrote:
> On Sat, 11 Mar 2023 17:07:24 +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>> 
>> Add bindings for the always-on clock and reset generator (AONCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>> 
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  .../clock/starfive,jh7110-aoncrg.yaml         | 107 ++++++++++++++++++
>>  .../dt-bindings/clock/starfive,jh7110-crg.h   |  18 +++
>>  .../dt-bindings/reset/starfive,jh7110-crg.h   |  12 ++
>>  3 files changed, 137 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
>> 
> 
> 
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
> 
> If a tag was not added on purpose, please state why and what changed.
> 
> Missing tags:
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

This patch has been changed a lot and I am not sure whether it's still
the one you want. So I removed the Reviewed-by tag.

Best regards,
Hal
Hal Feng March 19, 2023, 1:28 p.m. UTC | #4 
On Sat, 11 Mar 2023 13:14:45 +0000, Conor Dooley wrote:
> On Sat, Mar 11, 2023 at 05:07:24PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>> 
>> Add bindings for the always-on clock and reset generator (AONCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>> 
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
>> @@ -0,0 +1,107 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 Always-On Clock and Reset Generator
>> +
>> +maintainers:
>> +  - Emil Renner Berthing <kernel@esmil.dk>
>> +
>> +properties:
>> +  compatible:
>> +    const: starfive,jh7110-aoncrg
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    oneOf:
>> +      - items:
>> +          - description: Main Oscillator (24 MHz)
>> +          - description: GMAC0 RMII reference or GMAC0 RGMII RX
>> +          - description: STG AXI/AHB
>> +          - description: APB Bus
>> +          - description: GMAC0 GTX
>> +
>> +      - items:
>> +          - description: Main Oscillator (24 MHz)
>> +          - description: GMAC0 RMII reference or GMAC0 RGMII RX
>> +          - description: STG AXI/AHB or GMAC0 RGMII RX
>> +          - description: APB Bus or STG AXI/AHB
>> +          - description: GMAC0 GTX or APB Bus
>> +          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
> 
> Something tells me that the use of "or" means we're not doing this
> correctly.
> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

There are two possible cases when the number of clock inputs is 6:

Main Oscillator
GMAC0 RMII reference or GMAC0 RGMII RX
STG AXI/AHB
APB Bus
GMAC0 GTX
RTC Oscillator

and

Main Oscillator
GMAC0 RMII reference
GMAC0 RGMII RX
STG AXI/AHB
APB Bus
GMAC0 GTX

So I used the "or" in the items descriptions. Thanks.

Best regards,
Hal

> 
>> +      - items:
>> +          - description: Main Oscillator (24 MHz)
>> +          - description: GMAC0 RMII reference
>> +          - description: GMAC0 RGMII RX
>> +          - description: STG AXI/AHB
>> +          - description: APB Bus
>> +          - description: GMAC0 GTX
>> +          - description: RTC Oscillator (32.768 kHz)
>> +
>> +  clock-names:
>> +    oneOf:
>> +      - minItems: 5
>> +        items:
>> +          - const: osc
>> +          - enum:
>> +              - gmac0_rmii_refin
>> +              - gmac0_rgmii_rxin
>> +          - const: stg_axiahb
>> +          - const: apb_bus
>> +          - const: gmac0_gtxclk
>> +          - const: rtc_osc
>> +
>> +      - minItems: 6
>> +        items:
>> +          - const: osc
>> +          - const: gmac0_rmii_refin
>> +          - const: gmac0_rgmii_rxin
>> +          - const: stg_axiahb
>> +          - const: apb_bus
>> +          - const: gmac0_gtxclk
>> +          - const: rtc_osc
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
new file mode 100644
index 000000000000..923680a44aef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
@@ -0,0 +1,107 @@ 
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock and Reset Generator
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+  compatible:
+    const: starfive,jh7110-aoncrg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    oneOf:
+      - items:
+          - description: Main Oscillator (24 MHz)
+          - description: GMAC0 RMII reference or GMAC0 RGMII RX
+          - description: STG AXI/AHB
+          - description: APB Bus
+          - description: GMAC0 GTX
+
+      - items:
+          - description: Main Oscillator (24 MHz)
+          - description: GMAC0 RMII reference or GMAC0 RGMII RX
+          - description: STG AXI/AHB or GMAC0 RGMII RX
+          - description: APB Bus or STG AXI/AHB
+          - description: GMAC0 GTX or APB Bus
+          - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
+
+      - items:
+          - description: Main Oscillator (24 MHz)
+          - description: GMAC0 RMII reference
+          - description: GMAC0 RGMII RX
+          - description: STG AXI/AHB
+          - description: APB Bus
+          - description: GMAC0 GTX
+          - description: RTC Oscillator (32.768 kHz)
+
+  clock-names:
+    oneOf:
+      - minItems: 5
+        items:
+          - const: osc
+          - enum:
+              - gmac0_rmii_refin
+              - gmac0_rgmii_rxin
+          - const: stg_axiahb
+          - const: apb_bus
+          - const: gmac0_gtxclk
+          - const: rtc_osc
+
+      - minItems: 6
+        items:
+          - const: osc
+          - const: gmac0_rmii_refin
+          - const: gmac0_rgmii_rxin
+          - const: stg_axiahb
+          - const: apb_bus
+          - const: gmac0_gtxclk
+          - const: rtc_osc
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+  '#reset-cells':
+    const: 1
+    description:
+      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+    clock-controller@17000000 {
+        compatible = "starfive,jh7110-aoncrg";
+        reg = <0x17000000 0x10000>;
+        clocks = <&osc>, <&gmac0_rmii_refin>,
+                 <&gmac0_rgmii_rxin>,
+                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+                 <&syscrg JH7110_SYSCLK_APB_BUS>,
+                 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
+                 <&rtc_osc>;
+        clock-names = "osc", "gmac0_rmii_refin",
+                      "gmac0_rgmii_rxin", "stg_axiahb",
+                      "apb_bus", "gmac0_gtxclk",
+                      "rtc_osc";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index fdd1852e34cc..06257bfd9ac1 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -200,4 +200,22 @@ 
 
 #define JH7110_SYSCLK_END			190
 
+/* AONCRG clocks */
+#define JH7110_AONCLK_OSC_DIV4			0
+#define JH7110_AONCLK_APB_FUNC			1
+#define JH7110_AONCLK_GMAC0_AHB			2
+#define JH7110_AONCLK_GMAC0_AXI			3
+#define JH7110_AONCLK_GMAC0_RMII_RTX		4
+#define JH7110_AONCLK_GMAC0_TX			5
+#define JH7110_AONCLK_GMAC0_TX_INV		6
+#define JH7110_AONCLK_GMAC0_RX			7
+#define JH7110_AONCLK_GMAC0_RX_INV		8
+#define JH7110_AONCLK_OTPC_APB			9
+#define JH7110_AONCLK_RTC_APB			10
+#define JH7110_AONCLK_RTC_INTERNAL		11
+#define JH7110_AONCLK_RTC_32K			12
+#define JH7110_AONCLK_RTC_CAL			13
+
+#define JH7110_AONCLK_END			14
+
 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index b88216a4fe40..d78e38690ceb 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -139,4 +139,16 @@ 
 
 #define JH7110_SYSRST_END			126
 
+/* AONCRG resets */
+#define JH7110_AONRST_GMAC0_AXI			0
+#define JH7110_AONRST_GMAC0_AHB			1
+#define JH7110_AONRST_IOMUX			2
+#define JH7110_AONRST_PMU_APB			3
+#define JH7110_AONRST_PMU_WKUP			4
+#define JH7110_AONRST_RTC_APB			5
+#define JH7110_AONRST_RTC_CAL			6
+#define JH7110_AONRST_RTC_32K			7
+
+#define JH7110_AONRST_END			8
+
 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */