@@ -452,12 +452,6 @@ __und_usr:
@ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
@ faulting instruction depending on Thumb mode.
@ r3 = regs->ARM_cpsr
- @
- @ The emulation code returns using r9 if it has emulated the
- @ instruction, or the more conventional lr if we are to treat
- @ this as a real undefined instruction
- @
- badr r9, ret_from_exception
@ IRQs must be enabled before attempting to read the instruction from
@ user space since that could cause a page/translation fault if the
@@ -465,21 +459,8 @@ __und_usr:
enable_irq
tst r3, #PSR_T_BIT @ Thumb mode?
- bne __und_usr_thumb
- sub r4, r2, #4 @ ARM instr at LR - 4
-1: ldrt r0, [r4]
- ARM_BE8(rev r0, r0) @ little endian instruction
-
- uaccess_disable ip
-
- @ r0 = 32-bit ARM instruction which caused the exception
- @ r2 = PC value for the following instruction (:= regs->ARM_pc)
- @ r4 = PC value for the faulting instruction
- @ lr = 32-bit undefined instruction function
- badr lr, __und_usr_fault_32
- b call_fpe
+ beq call_fpe
-__und_usr_thumb:
@ Thumb instruction
sub r4, r2, #2 @ First half of thumb instr at LR - 2
#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
@@ -501,22 +482,14 @@ __und_usr_thumb:
*/
.arch armv6t2
#endif
-2: ldrht r5, [r4]
+USERL( 4f, ldrht r5, [r4])
ARM_BE8(rev16 r5, r5) @ little endian instruction
cmp r5, #0xe800 @ 32bit instruction if xx != 0
- blo __und_usr_fault_16_pan @ 16bit undefined instruction
-3: ldrht r0, [r2]
-ARM_BE8(rev16 r0, r0) @ little endian instruction
uaccess_disable ip
+ blo __und_usr_fault_16 @ 16bit undefined instruction
add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
- orr r0, r0, r5, lsl #16
- badr lr, __und_usr_fault_32
- @ r0 = the two 16-bit Thumb instructions which caused the exception
- @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
- @ r4 = PC value for the first 16-bit Thumb instruction
- @ lr = 32bit undefined instruction function
-
+ b __und_usr_fault_32
#if __LINUX_ARM_ARCH__ < 7
/* If the target arch was overridden, change it back: */
#ifdef CONFIG_CPU_32v6K
@@ -537,14 +510,7 @@ ENDPROC(__und_usr)
.pushsection .text.fixup, "ax"
.align 2
4: str r4, [sp, #S_PC] @ retry current instruction
- ret r9
- .popsection
- .pushsection __ex_table,"a"
- .long 1b, 4b
-#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
- .long 2b, 4b
- .long 3b, 4b
-#endif
+ b ret_from_exception
.popsection
/*
@@ -558,17 +524,23 @@ ENDPROC(__und_usr)
* for the ARM6/ARM7 SWI bug.
*
* Emulators may wish to make use of the following registers:
- * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
+ * r0 = instruction opcode (32-bit ARM)
* r2 = PC value to resume execution after successful emulation
* r9 = normal "successful" return address
* r10 = this threads thread_info structure
* lr = unrecognised instruction return address
* IRQs enabled, FIQs enabled.
*/
- @
- @ Fall-through from Thumb-2 __und_usr
- @
call_fpe:
+ badr r9, ret_from_exception
+ badr lr, __und_usr_fault_32
+
+ sub r4, r2, #4 @ ARM instr at LR - 4
+USERL( 4b, ldrt r0, [r4])
+ARM_BE8(rev r0, r0) @ little endian instruction
+
+ uaccess_disable ip
+
get_thread_info r10 @ get current thread
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
@@ -630,13 +602,11 @@ ENDPROC(no_fp)
__und_usr_fault_32:
mov r1, #4
b 1f
-__und_usr_fault_16_pan:
- uaccess_disable ip
__und_usr_fault_16:
mov r1, #2
1: mov r0, sp
- badr lr, ret_from_exception
- b __und_fault
+ bl __und_fault
+ b ret_from_exception
ENDPROC(__und_usr_fault_32)
ENDPROC(__und_usr_fault_16)
Now that the only remaining coprocessor instructions being handled via the dispatch in entry-armv.S are ones that only exist in a ARM (A32) encoding, we can simplify the handling of Thumb undef exceptions, and send them straight to the undefined instruction handlers in C code. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> --- arch/arm/kernel/entry-armv.S | 64 ++++++-------------- 1 file changed, 17 insertions(+), 47 deletions(-)