| Message ID | 20230320190520.124513-2-arinc.unal@arinc9.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [net,1/3] net: dsa: mt7530: move enabling disabling core clock to mt7530_pll_setup() | expand |
On Mon, 20 Mar 2023 22:05:19 +0300 arinc9.unal@gmail.com wrote: > I asked this before, MT7530 DSA driver maintainers, please explain the code > I mentioned on the second paragraph. > > I intend to send a patch to remove the maintainers, Sean Wang, Landen Chao > DENG Qingfang, listed on the MAINTAINERS file and change the status to > orphan if none of them respond to this question or review the patches. Sounds fair.
On Mon, 2023-03-20 at 22:05 +0300, arinc9.unal@gmail.com wrote: > > I asked this before, MT7530 DSA driver maintainers, please explain > the code > I mentioned on the second paragraph. > > --- > @@ -2207,6 +2198,15 @@ mt7530_setup(struct dsa_switch *ds) > > mt7530_pll_setup(priv); > > + /* Lower Tx driving for TRGMII path */ > + for (i = 0; i < NUM_TRGMII_CTRL; i++) > + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), > + TD_DM_DRVP(8) | TD_DM_DRVN(8)); > + I guess you ask this part, and I try my best to recall what the original author said years ago. It is used to adjust the RX delay of port 6 to match the tx signal of the link partner. > + for (i = 0; i < NUM_TRGMII_CTRL; i++) > + mt7530_rmw(priv, MT7530_TRGMII_RD(i), > + RD_TAP_MASK, RD_TAP(16)); > + > >
On 26 March 2023 21:13:49 GMT+03:00, "Landen Chao (趙皎宏)" <Landen.Chao@mediatek.com> wrote: >On Mon, 2023-03-20 at 22:05 +0300, arinc9.unal@gmail.com wrote: >> >> I asked this before, MT7530 DSA driver maintainers, please explain >> the code >> I mentioned on the second paragraph. >> >> --- >> @@ -2207,6 +2198,15 @@ mt7530_setup(struct dsa_switch *ds) >> >> mt7530_pll_setup(priv); >> >> + /* Lower Tx driving for TRGMII path */ >> + for (i = 0; i < NUM_TRGMII_CTRL; i++) >> + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), >> + TD_DM_DRVP(8) | TD_DM_DRVN(8)); >> + >I guess you ask this part, and I try my best to recall what the >original author said years ago. >It is used to adjust the RX delay of port 6 to match the tx >signal of the link partner. Ok, thanks for replying. I will move this at the end, inside 'if (trgint)'. Since this doesn't lower the driving, there's no apparent benefit to run this if trgmii is not being used. Arınç
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index d4a559007973..8831bd409a40 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -419,12 +419,12 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } -/* Setup TX circuit including relevant PAD and driving */ +/* Setup port 6 interface mode and TRGMII TX circuit */ static int mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - u32 ncpo1, ssc_delta, trgint, i, xtal; + u32 ncpo1, ssc_delta, trgint, xtal; xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; @@ -469,11 +469,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) P6_INTF_MODE(trgint)); if (trgint) { - /* Lower Tx Driving for TRGMII path */ - for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) - mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), - TD_DM_DRVP(8) | TD_DM_DRVN(8)); - /* Disable the MT7530 TRGMII clocks */ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); @@ -494,10 +489,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); - } else { - for (i = 0 ; i < NUM_TRGMII_CTRL; i++) - mt7530_rmw(priv, MT7530_TRGMII_RD(i), - RD_TAP_MASK, RD_TAP(16)); } return 0; @@ -2207,6 +2198,15 @@ mt7530_setup(struct dsa_switch *ds) mt7530_pll_setup(priv); + /* Lower Tx driving for TRGMII path */ + for (i = 0; i < NUM_TRGMII_CTRL; i++) + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), + TD_DM_DRVP(8) | TD_DM_DRVN(8)); + + for (i = 0; i < NUM_TRGMII_CTRL; i++) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); + /* Enable port 6 */ val = mt7530_read(priv, MT7530_MHWTRAP); val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;