Message ID | 20230309145246.22787-9-joey.gouly@arm.com (mailing list archive) |
---|---|
State | New, archived |
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Thu, 9 Mar 2023 14:52:53 +0000 From: Joey Gouly <joey.gouly@arm.com> To: <linux-arm-kernel@lists.infradead.org> CC: <nd@arm.com>, <broonie@kernel.org>, <catalin.marinas@arm.com>, <james.morse@arm.com>, <joey.gouly@arm.com>, <mark.rutland@arm.com>, <maz@kernel.org>, <oliver.upton@linux.dev>, <suzuki.poulose@arm.com>, <will@kernel.org>, <yuzenghui@huawei.com> Subject: [PATCH v1 08/18] arm64: cpufeature: add Permission Indirection Extension cpucap Date: Thu, 9 Mar 2023 14:52:36 +0000 Message-ID: <20230309145246.22787-9-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230309145246.22787-1-joey.gouly@arm.com> References: <20230309145246.22787-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: VI1EUR03FT059:EE_|GV2PR08MB8320:EE_|VI1EUR03FT064:EE_|AS8PR08MB6533:EE_ X-MS-Office365-Filtering-Correlation-Id: 03ba7c7d-fd5c-4812-57dc-08db20ae0392 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Permission Indirection Extension
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On Thu, Mar 09, 2023 at 02:52:36PM +0000, Joey Gouly wrote: > This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE > as the boot CPU will enable PIE if it has it, so secondary CPUs must also > have this feature. In theory I think we could combine them CPUs with and without PIE (possibly a slight issue with DBM) but it's not worth the effort. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6944d8bbb17c..acbc21963128 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2793,6 +2793,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .min_field_value = ID_AA64MMFR3_EL1_TCRX_IMP, .matches = has_cpuid_feature, }, + { + .desc = "Permission Indirection Extension (PIE)", + .capability = ARM64_HAS_PIE, + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, + .sys_reg = SYS_ID_AA64MMFR3_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR3_EL1_S1PIE_SHIFT, + .field_width = 4, + .min_field_value = ID_AA64MMFR3_EL1_S1PIE_IMP, + .matches = has_cpuid_feature, + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 5859b9ee7444..c4c4c59882b8 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -37,6 +37,7 @@ HAS_NESTED_VIRT HAS_NO_FPSIMD HAS_NO_HW_PREFETCH HAS_PAN +HAS_PIE HAS_RAS_EXTN HAS_RNG HAS_SB
This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE as the boot CPU will enable PIE if it has it, so secondary CPUs must also have this feature. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 12 insertions(+)