| Message ID | 20230323233735.2131020-5-vladimir.zapolskiy@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: add QCE on SM8250 and SM8450 platforms | expand |
On Fri, 24 Mar 2023 at 05:07, Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> wrote: > > Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 7b78761f2041..363818da792a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2222,6 +2222,30 @@ ufs_mem_phy_lanes: phy@1d87400 { > }; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x0 0x01dc4000 0x0 0x24000>; > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <8>; > + qcom,num-ees = <2>; > + iommus = <&apps_smmu 0x586 0x11>, > + <&apps_smmu 0x596 0x11>; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; > + reg = <0x0 0x01dfa000 0x0 0x6000>; > + dmas = <&cryptobam 6>, <&cryptobam 7>; > + dma-names = "rx", "tx"; > + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; > + interconnect-names = "memory"; > + iommus = <&apps_smmu 0x586 0x11>, > + <&apps_smmu 0x596 0x11>; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x40000>; > -- > 2.33.0 Already folded this patch (which includes your SoB) and sent via [1], which includes the correct BAM DMA compatible list. [1]. https://lore.kernel.org/linux-arm-msm/20230322114519.3412469-9-bhupesh.sharma@linaro.org/ Thanks.
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7b78761f2041..363818da792a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2222,6 +2222,30 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x24000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x586 0x11>, + <&apps_smmu 0x596 0x11>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + iommus = <&apps_smmu 0x586 0x11>, + <&apps_smmu 0x596 0x11>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>;
Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)