| Message ID | 20230203-evk-board-support-v3-12-0003e80e0095@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Improve the MT8365 SoC and EVK board support | expand |
Il 29/03/23 10:54, Alexandre Mergnat ha scritto: > This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards. > It supports power management with Energy Efficient Ethernet and Wake-on-LAN > specification. Flow control is provided for half-duplex and full-duplex > mode. For packet transmission and reception, the controller supports > IPv4/UDP/TCP checksum offload and VLAN tag insertion. > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 29/03/2023 10:54, Alexandre Mergnat wrote: > This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards. > It supports power management with Energy Efficient Ethernet and Wake-on-LAN > specification. Flow control is provided for half-duplex and full-duplex > mode. For packet transmission and reception, the controller supports > IPv4/UDP/TCP checksum offload and VLAN tag insertion. > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Applied thanks! > --- > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > index a67eeca28da5..394a5a61be59 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -438,6 +438,18 @@ mmc2: mmc@11250000 { > status = "disabled"; > }; > > + ethernet: ethernet@112a0000 { > + compatible = "mediatek,mt8365-eth"; > + reg = <0 0x112a0000 0 0x1000>; > + mediatek,pericfg = <&infracfg>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&topckgen CLK_TOP_ETH_SEL>, > + <&infracfg CLK_IFR_NIC_AXI>, > + <&infracfg CLK_IFR_NIC_SLV_AXI>; > + clock-names = "core", "reg", "trans"; > + status = "disabled"; > + }; > + > u3phy: t-phy@11cc0000 { > compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; > #address-cells = <1>; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index a67eeca28da5..394a5a61be59 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -438,6 +438,18 @@ mmc2: mmc@11250000 { status = "disabled"; }; + ethernet: ethernet@112a0000 { + compatible = "mediatek,mt8365-eth"; + reg = <0 0x112a0000 0 0x1000>; + mediatek,pericfg = <&infracfg>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>;
This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards. It supports power management with Energy Efficient Ethernet and Wake-on-LAN specification. Flow control is provided for half-duplex and full-duplex mode. For packet transmission and reception, the controller supports IPv4/UDP/TCP checksum offload and VLAN tag insertion. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)