| Message ID | 20230331062521.529005-2-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PHY-GMII-SEL: Add support for J784S4 SoC | expand |
On 31/03/2023 09:25, Siddharth Vadapalli wrote: > Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. > > Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" > property for J784S4. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c > index c87118cb2af9..fba5c0c0771c 100644 > --- a/drivers/phy/ti/phy-gmii-sel.c > +++ b/drivers/phy/ti/phy-gmii-sel.c > @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { > .num_qsgmii_main_ports = 2, > }; > > +static const > +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { Please make it into one line > + .use_of_data = true, > + .regfields = phy_gmii_sel_fields_am654, > + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), > + .num_ports = 8, > + .num_qsgmii_main_ports = 2, > +}; > + > static const struct of_device_id phy_gmii_sel_id_table[] = { > { > .compatible = "ti,am3352-phy-gmii-sel", > @@ -264,6 +273,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = { > .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", > .data = &phy_gmii_sel_cpsw9g_soc_j721e, > }, > + { > + .compatible = "ti,j784s4-cpsw9g-phy-gmii-sel", > + .data = &phy_gmii_sel_cpsw9g_soc_j784s4, > + }, > {} > }; > MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); -- cheers, -roger
Hello Roger, On 31/03/23 13:15, Roger Quadros wrote: > > > On 31/03/2023 09:25, Siddharth Vadapalli wrote: >> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. >> >> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" >> property for J784S4. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c >> index c87118cb2af9..fba5c0c0771c 100644 >> --- a/drivers/phy/ti/phy-gmii-sel.c >> +++ b/drivers/phy/ti/phy-gmii-sel.c >> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { >> .num_qsgmii_main_ports = 2, >> }; >> >> +static const >> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { > > Please make it into one line I was simply following the convention used for other SoC data structs in the same file. Please let me know why this has to be an exception and I will post the v2 series with the change accordingly. Regards, Siddharth.
On 31/03/2023 10:49, Siddharth Vadapalli wrote: > Hello Roger, > > On 31/03/23 13:15, Roger Quadros wrote: >> >> >> On 31/03/2023 09:25, Siddharth Vadapalli wrote: >>> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. >>> >>> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" >>> property for J784S4. >>> >>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >>> --- >>> drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ >>> 1 file changed, 13 insertions(+) >>> >>> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c >>> index c87118cb2af9..fba5c0c0771c 100644 >>> --- a/drivers/phy/ti/phy-gmii-sel.c >>> +++ b/drivers/phy/ti/phy-gmii-sel.c >>> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { >>> .num_qsgmii_main_ports = 2, >>> }; >>> >>> +static const >>> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { >> >> Please make it into one line > > I was simply following the convention used for other SoC data structs in the > same file. Please let me know why this has to be an exception and I will post > the v2 series with the change accordingly. Not that much of a deal. ;) Reviewed-by: Roger Quadros <rogerq@kernel.org>
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index c87118cb2af9..fba5c0c0771c 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { .num_qsgmii_main_ports = 2, }; +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { + .use_of_data = true, + .regfields = phy_gmii_sel_fields_am654, + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .num_ports = 8, + .num_qsgmii_main_ports = 2, +}; + static const struct of_device_id phy_gmii_sel_id_table[] = { { .compatible = "ti,am3352-phy-gmii-sel", @@ -264,6 +273,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = { .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", .data = &phy_gmii_sel_cpsw9g_soc_j721e, }, + { + .compatible = "ti,j784s4-cpsw9g-phy-gmii-sel", + .data = &phy_gmii_sel_cpsw9g_soc_j784s4, + }, {} }; MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)