| Message ID | 20230315092408.1722114-1-s-vadapalli@ti.com |
|---|---|
| State | Accepted |
| Commit | 73b46467cac027fe6cbe6585946726b53b80bfdb |
| Headers | show |
| Series | dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G | expand |
On 15/03/2023 10:24, Siddharth Vadapalli wrote: > The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports > additional PHY modes like QSGMII. Add a compatible for it. > > Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++ > 1 file changed, 4 insertions(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hello Vinod, Can this patch please be merged in case of no concerns? Regards, Siddharth. On 19/03/23 18:15, Krzysztof Kozlowski wrote: > On 15/03/2023 10:24, Siddharth Vadapalli wrote: >> The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports >> additional PHY modes like QSGMII. Add a compatible for it. >> >> Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G. >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++ >> 1 file changed, 4 insertions(+) > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Best regards, > Krzysztof >
On 15-03-23, 14:54, Siddharth Vadapalli wrote: > The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports > additional PHY modes like QSGMII. Add a compatible for it. > > Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G. Applied, thanks
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index 6d46f57fa1b4..3f2c5e2a11d5 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -55,6 +55,7 @@ properties: - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel reg: maxItems: 1 @@ -87,6 +88,7 @@ allOf: - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: '#phy-cells': @@ -113,6 +115,7 @@ allOf: contains: enum: - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: @@ -130,6 +133,7 @@ allOf: enum: - ti,j7200-cpsw5g-phy-gmii-sel - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: false
The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports additional PHY modes like QSGMII. Add a compatible for it. Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 ++++ 1 file changed, 4 insertions(+)