| Message ID | 20230331215804.783439-3-ahalaney@redhat.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add EMAC3 support for sa8540p-ride (devicetree/clk bits) | expand |
On 31.03.2023 23:58, Andrew Halaney wrote: > This platform has 2 MACs integrated in it, go ahead and describe them. > > Signed-off-by: Andrew Halaney <ahalaney@redhat.com> > --- > > Changes since v2: > * Fix spacing (Konrad) > > Changes since v1: > * None > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 59 ++++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 42bfa9fa5b96..f28ea86b128d 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -761,6 +761,65 @@ soc: soc@0 { > ranges = <0 0 0 0 0x10 0>; > dma-ranges = <0 0 0 0 0x10 0>; > > + ethernet0: ethernet@20000 { > + compatible = "qcom,sc8280xp-ethqos"; > + reg = <0x0 0x00020000 0x0 0x10000>, > + <0x0 0x00036000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC0_AXI_CLK>, > + <&gcc GCC_EMAC0_SLV_AHB_CLK>, > + <&gcc GCC_EMAC0_PTP_CLK>, > + <&gcc GCC_EMAC0_RGMII_CLK>; > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "rgmii"; > + > + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_lpi"; > + iommus = <&apps_smmu 0x4c0 0xf>; > + power-domains = <&gcc EMAC_0_GDSC>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <4096>; > + tx-fifo-depth = <4096>; > + > + status = "disabled"; > + }; > + > + ethernet1: ethernet@23000000 { Nodes under /soc should be ordered by their unit address, so in this case it belongs after dispcc1: clock-controller@.. With that fixed: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > + compatible = "qcom,sc8280xp-ethqos"; > + reg = <0x0 0x23000000 0x0 0x10000>, > + <0x0 0x23016000 0x0 0x100>; > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC1_AXI_CLK>, > + <&gcc GCC_EMAC1_SLV_AHB_CLK>, > + <&gcc GCC_EMAC1_PTP_CLK>, > + <&gcc GCC_EMAC1_RGMII_CLK>; > + clock-names = "stmmaceth", > + "pclk", > + "ptp_ref", > + "rgmii"; > + > + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_lpi"; > + > + iommus = <&apps_smmu 0x40 0xf>; > + power-domains = <&gcc EMAC_1_GDSC>; > + > + snps,tso; > + snps,pbl = <32>; > + rx-fifo-depth = <4096>; > + tx-fifo-depth = <4096>; > + > + status = "disabled"; > + }; > + > gcc: clock-controller@100000 { > compatible = "qcom,gcc-sc8280xp"; > reg = <0x0 0x00100000 0x0 0x1f0000>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 42bfa9fa5b96..f28ea86b128d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -761,6 +761,65 @@ soc: soc@0 { ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; + ethernet0: ethernet@20000 { + compatible = "qcom,sc8280xp-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; + iommus = <&apps_smmu 0x4c0 0xf>; + power-domains = <&gcc EMAC_0_GDSC>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + + ethernet1: ethernet@23000000 { + compatible = "qcom,sc8280xp-ethqos"; + reg = <0x0 0x23000000 0x0 0x10000>, + <0x0 0x23016000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; + + iommus = <&apps_smmu 0x40 0xf>; + power-domains = <&gcc EMAC_1_GDSC>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,gcc-sc8280xp"; reg = <0x0 0x00100000 0x0 0x1f0000>;
This platform has 2 MACs integrated in it, go ahead and describe them. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> --- Changes since v2: * Fix spacing (Konrad) Changes since v1: * None arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)