| Message ID | 20230404020653.18911-3-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Fix pointer mask related support | expand |
On Tue, Apr 4, 2023 at 12:08 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > write_mstatus() can only change current xl when in debug mode. > And we need update cur_pmmask/base in this case. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d522efc0b6..43b9ad4500 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1277,8 +1277,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, > mstatus = set_field(mstatus, MSTATUS64_SXL, xl); > } > env->mstatus = mstatus; > - env->xl = cpu_recompute_xl(env); > > + /* > + * Except in debug mode, UXL/SXL can only be modified by higher > + * privilege mode. So xl will not be changed in normal mode. > + */ > + if (env->debugger) { > + env->xl = cpu_recompute_xl(env); > + riscv_cpu_update_mask(env); > + } > return RISCV_EXCP_NONE; > } > > -- > 2.25.1 > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b6..43b9ad4500 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1277,8 +1277,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = set_field(mstatus, MSTATUS64_SXL, xl); } env->mstatus = mstatus; - env->xl = cpu_recompute_xl(env); + /* + * Except in debug mode, UXL/SXL can only be modified by higher + * privilege mode. So xl will not be changed in normal mode. + */ + if (env->debugger) { + env->xl = cpu_recompute_xl(env); + riscv_cpu_update_mask(env); + } return RISCV_EXCP_NONE; }