| Message ID | 20230405111412.151192-5-j-choudhary@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add peripherals for J784S4 | expand |
On 4/5/23 6:14 AM, Jayesh Choudhary wrote: > From: Rahul T R <r-ravikumar@ti.com> > > Add DSS node for J784S4 SoC. DSS IP in J784S4 > is same as DSS IP in J721E, so same compatible is > being used. > Also add assigned clks for DSS > > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 11 +++++ The changes to `k3-j784s4-evm.dts` in this patch and the next all need moved to the last patch in this series. All these changes needed to enable the display in the EVM work together and so should be one atomic step. Andrew > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 55 ++++++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > index b1445b7c2aa8..ccbfca76e9ae 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > @@ -305,3 +305,14 @@ &main_cpsw1_port1 { > &serdes_refclk { > clock-frequency = <100000000>; > }; > + > +&dss { > + assigned-clocks = <&k3_clks 218 2>, > + <&k3_clks 218 5>, > + <&k3_clks 218 14>, > + <&k3_clks 218 18>; > + assigned-clock-parents = <&k3_clks 218 3>, > + <&k3_clks 218 7>, > + <&k3_clks 218 16>, > + <&k3_clks 218 22>; > +}; > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 0cd692bc52e6..86ce6f6d4fc2 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -1373,4 +1373,59 @@ main_spi7: spi@2170000 { > clocks = <&k3_clks 383 1>; > status = "disabled"; > }; > + > + dss: dss@4a00000 { > + compatible = "ti,j721e-dss"; > + reg = > + <0x00 0x04a00000 0x00 0x10000>, > + <0x00 0x04a10000 0x00 0x10000>, > + <0x00 0x04b00000 0x00 0x10000>, > + <0x00 0x04b10000 0x00 0x10000>, > + > + <0x00 0x04a20000 0x00 0x10000>, > + <0x00 0x04a30000 0x00 0x10000>, > + <0x00 0x04a50000 0x00 0x10000>, > + <0x00 0x04a60000 0x00 0x10000>, > + > + <0x00 0x04a70000 0x00 0x10000>, > + <0x00 0x04a90000 0x00 0x10000>, > + <0x00 0x04ab0000 0x00 0x10000>, > + <0x00 0x04ad0000 0x00 0x10000>, > + > + <0x00 0x04a80000 0x00 0x10000>, > + <0x00 0x04aa0000 0x00 0x10000>, > + <0x00 0x04ac0000 0x00 0x10000>, > + <0x00 0x04ae0000 0x00 0x10000>, > + <0x00 0x04af0000 0x00 0x10000>; > + > + reg-names = "common_m", "common_s0", > + "common_s1", "common_s2", > + "vidl1", "vidl2","vid1","vid2", > + "ovr1", "ovr2", "ovr3", "ovr4", > + "vp1", "vp2", "vp3", "vp4", > + "wb"; > + > + clocks = <&k3_clks 218 0>, > + <&k3_clks 218 2>, > + <&k3_clks 218 5>, > + <&k3_clks 218 14>, > + <&k3_clks 218 18>; > + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; > + > + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; > + > + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "common_m", > + "common_s0", > + "common_s1", > + "common_s2"; > + > + status = "disabled"; > + > + dss_ports: ports { > + }; > + }; > };
Hello Andrew, On 05/04/23 22:07, Andrew Davis wrote: > On 4/5/23 6:14 AM, Jayesh Choudhary wrote: >> From: Rahul T R <r-ravikumar@ti.com> >> >> Add DSS node for J784S4 SoC. DSS IP in J784S4 >> is same as DSS IP in J721E, so same compatible is >> being used. >> Also add assigned clks for DSS >> >> Signed-off-by: Rahul T R <r-ravikumar@ti.com> >> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 11 +++++ > > > The changes to `k3-j784s4-evm.dts` in this patch and the next all > need moved to the last patch in this series. All these changes > needed to enable the display in the EVM work together and so > should be one atomic step. > > Andrew Okay. Will fix this in v2. -Jayesh > >> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 55 ++++++++++++++++++++++ >> 2 files changed, 66 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts >> b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts >> index b1445b7c2aa8..ccbfca76e9ae 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts >> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts >> @@ -305,3 +305,14 @@ &main_cpsw1_port1 { >> &serdes_refclk { >> clock-frequency = <100000000>; >> }; [...]
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index b1445b7c2aa8..ccbfca76e9ae 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -305,3 +305,14 @@ &main_cpsw1_port1 { &serdes_refclk { clock-frequency = <100000000>; }; + +&dss { + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 0cd692bc52e6..86ce6f6d4fc2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1373,4 +1373,59 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 383 1>; status = "disabled"; }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = + <0x00 0x04a00000 0x00 0x10000>, + <0x00 0x04a10000 0x00 0x10000>, + <0x00 0x04b00000 0x00 0x10000>, + <0x00 0x04b10000 0x00 0x10000>, + + <0x00 0x04a20000 0x00 0x10000>, + <0x00 0x04a30000 0x00 0x10000>, + <0x00 0x04a50000 0x00 0x10000>, + <0x00 0x04a60000 0x00 0x10000>, + + <0x00 0x04a70000 0x00 0x10000>, + <0x00 0x04a90000 0x00 0x10000>, + <0x00 0x04ab0000 0x00 0x10000>, + <0x00 0x04ad0000 0x00 0x10000>, + + <0x00 0x04a80000 0x00 0x10000>, + <0x00 0x04aa0000 0x00 0x10000>, + <0x00 0x04ac0000 0x00 0x10000>, + <0x00 0x04ae0000 0x00 0x10000>, + <0x00 0x04af0000 0x00 0x10000>; + + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + + clocks = <&k3_clks 218 0>, + <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + + status = "disabled"; + + dss_ports: ports { + }; + }; };